1Freescale MPC832XEMDS Board
2-----------------------------------------
31. Board Switches and Jumpers
41.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board
5	For some reason, the HW designers describe the switch settings
6	in terms of 0 and 1, and then map that to physical switches where
7	the label "On" refers to logic 0 and "Off" is logic 1.
8
9	Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
10	bits may contribute to signals that are numbered based at 0,
11	and some of those signals may be high-bit-number-0 too.  Heed
12	well the names and labels and do not get confused.
13
14		"Off" == 1
15		"On"  == 0
16
17	SW3 is switch 18 as silk-screened onto the board.
18	SW4[8] is the bit labeled 8 on Switch 4.
19	SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5.
20	SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6.
21	SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
22		and bits labeled 8 is set as "Off".
23
241.1 For the MPC832XEMDS PROTO Board
25
26	First, make sure the board default setting is consistent with the document
27		 shipped with your board. Then apply the following setting:
28	SW3[1-8]= 0000_1000  (core PLL setting, core enable)
29	SW4[1-8]= 0001_0010  (Flash boot on local bus, system PLL setting)
30	SW5[1-8]= 0010_0110  (Boot from high end)
31	SW6[1-8]= 0011_0100  (Flash boot on 16 bit local bus)
32	SW7[1-8]= 1000_0011  (QE PLL setting)
33
34	ENET3/4 MII mode settings:
35	J1 1-2 (ETH3_TXER)
36	J2 2-3 (MII mode)
37	J3 2-3 (MII mode)
38	J4 2-3 (ADSL clockOscillator)
39	J5 1-2 (ETH4_TXER)
40	J6 2-3 (ClockOscillator)
41	JP1 removed (don't force PORESET)
42	JP2 mounted (ETH4/2 MII)
43	JP3 mounted (ETH3 MII)
44	JP4 mounted (HRCW from BCSR)
45
46	ENET3/4 RMII mode settings:
47	J1 1-2 (ETH3_TXER)
48	J2 1-2 (RMII mode)
49	J3 1-2 (RMII mode)
50	J4 2-3 (ADSL clockOscillator)
51	J5 1-2 (ETH4_TXER)
52	J6 2-3 (ClockOscillator)
53	JP1 removed (don't force PORESET)
54	JP2 removed (ETH4/2 RMII)
55	JP3 removed (ETH3 RMII)
56	JP4 removed (HRCW from FLASH)
57
58	on board Oscillator: 66M
59
60
612. Memory Map
62
632.1 The memory map should look pretty much like this:
64
65	0x0000_0000	0x7fff_ffff	DDR			2G
66	0x8000_0000	0x8fff_ffff	PCI MEM prefetch	256M
67	0x9000_0000	0x9fff_ffff	PCI MEM non-prefetch	256M
68	0xc000_0000	0xdfff_ffff	Empty			512M
69	0xe000_0000	0xe01f_ffff	Int Mem Reg Space	2M
70	0xe020_0000	0xe02f_ffff	Empty			1M
71	0xe030_0000	0xe03f_ffff	PCI IO			1M
72	0xe040_0000	0xefff_ffff	Empty			252M
73	0xf400_0000	0xf7ff_ffff	Empty			64M
74	0xf800_0000	0xf800_7fff	BCSR on CS1		32K
75	0xf800_8000	0xf800_ffff	PIB CS2			32K
76	0xf801_0000	0xf801_7fff	PIB CS3			32K
77	0xfe00_0000	0xfeff_ffff	FLASH on CS0		16M
78
79
803. Definitions
81
823.1 Explanation of NEW definitions in:
83
84	include/configs/MPC832XEPB.h
85
86    CONFIG_MPC83xx	MPC83xx family for MPC8349, MPC8360 and MPC832x
87    CONFIG_MPC832x	MPC832x specific
88    CONFIG_MPC832XEMDS	MPC832XEMDS board specific
89
904. Compilation
91
92	Assuming you're using BASH shell:
93
94		export CROSS_COMPILE=your-cross-compile-prefix
95		cd u-boot
96		make distclean
97		make MPC832XEMDS_config
98		make
99
100	MPC832x support PCI 33MHz and PCI 66MHz, to make u-boot support PCI:
101
102		1)Make sure the DIP SW support PCI mode as described in Section 1.1.
103
104		2)To Make U-Boot image support PCI 33MHz, use
105			Make MPC832XEMDS_HOST_33_config
106
107		3)To Make U-Boot image support PCI 66MHz, use
108			Make MPC832XEMDS_HOST_66M_config
109
1105. Downloading and Flashing Images
111
1125.0 Download over network:
113
114	tftp 10000 u-boot.bin
115
1165.1 Reflash U-boot Image using U-boot
117
118	tftp 20000 u-boot.bin
119	protect off fe000000 fe0fffff
120	erase fe000000 fe0fffff
121	cp.b 20000 fe000000 xxxx
122
123You have to supply the correct byte count with 'xxxx' from the TFTP result log.
124Maybe 3ffff will work too, that corresponds to the erased sectors.
125
126
1276. Notes
128	1) The console baudrate for MPC832XEMDS is 115200bps.
129