1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * 4 * Michael Barkowski <michael.barkowski@freescale.com> 5 * Based on mpc832xmds file by Dave Liu <daveliu@freescale.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published 9 * by the Free Software Foundation. 10 */ 11 12 #include <common.h> 13 #include <ioports.h> 14 #include <mpc83xx.h> 15 #include <i2c.h> 16 #include <miiphy.h> 17 #include <command.h> 18 #include <libfdt.h> 19 #if defined(CONFIG_PCI) 20 #include <pci.h> 21 #endif 22 #include <asm/mmu.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 const qe_iop_conf_t qe_iop_conf_tab[] = { 27 /* UCC3 */ 28 {1, 0, 1, 0, 1}, /* TxD0 */ 29 {1, 1, 1, 0, 1}, /* TxD1 */ 30 {1, 2, 1, 0, 1}, /* TxD2 */ 31 {1, 3, 1, 0, 1}, /* TxD3 */ 32 {1, 9, 1, 0, 1}, /* TxER */ 33 {1, 12, 1, 0, 1}, /* TxEN */ 34 {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */ 35 36 {1, 4, 2, 0, 1}, /* RxD0 */ 37 {1, 5, 2, 0, 1}, /* RxD1 */ 38 {1, 6, 2, 0, 1}, /* RxD2 */ 39 {1, 7, 2, 0, 1}, /* RxD3 */ 40 {1, 8, 2, 0, 1}, /* RxER */ 41 {1, 10, 2, 0, 1}, /* RxDV */ 42 {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */ 43 {1, 11, 2, 0, 1}, /* COL */ 44 {1, 13, 2, 0, 1}, /* CRS */ 45 46 /* UCC2 */ 47 {0, 18, 1, 0, 1}, /* TxD0 */ 48 {0, 19, 1, 0, 1}, /* TxD1 */ 49 {0, 20, 1, 0, 1}, /* TxD2 */ 50 {0, 21, 1, 0, 1}, /* TxD3 */ 51 {0, 27, 1, 0, 1}, /* TxER */ 52 {0, 30, 1, 0, 1}, /* TxEN */ 53 {3, 23, 2, 0, 1}, /* TxCLK->CLK3 */ 54 55 {0, 22, 2, 0, 1}, /* RxD0 */ 56 {0, 23, 2, 0, 1}, /* RxD1 */ 57 {0, 24, 2, 0, 1}, /* RxD2 */ 58 {0, 25, 2, 0, 1}, /* RxD3 */ 59 {0, 26, 1, 0, 1}, /* RxER */ 60 {0, 28, 2, 0, 1}, /* Rx_DV */ 61 {3, 21, 2, 0, 1}, /* RxCLK->CLK16 */ 62 {0, 29, 2, 0, 1}, /* COL */ 63 {0, 31, 2, 0, 1}, /* CRS */ 64 65 {3, 4, 3, 0, 2}, /* MDIO */ 66 {3, 5, 1, 0, 2}, /* MDC */ 67 68 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ 69 }; 70 71 int fixed_sdram(void); 72 73 int dram_init(void) 74 { 75 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; 76 u32 msize = 0; 77 78 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) 79 return -ENXIO; 80 81 /* DDR SDRAM - Main SODIMM */ 82 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; 83 84 msize = fixed_sdram(); 85 86 /* set total bus SDRAM size(bytes) -- DDR */ 87 gd->ram_size = msize * 1024 * 1024; 88 89 return 0; 90 } 91 92 /************************************************************************* 93 * fixed sdram init -- doesn't use serial presence detect. 94 ************************************************************************/ 95 int fixed_sdram(void) 96 { 97 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; 98 u32 msize = 0; 99 u32 ddr_size; 100 u32 ddr_size_log2; 101 102 msize = CONFIG_SYS_DDR_SIZE; 103 for (ddr_size = msize << 20, ddr_size_log2 = 0; 104 (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { 105 if (ddr_size & 1) { 106 return -1; 107 } 108 } 109 im->sysconf.ddrlaw[0].ar = 110 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); 111 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; 112 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; 113 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; 114 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 115 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 116 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 117 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 118 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; 119 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; 120 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; 121 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; 122 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; 123 __asm__ __volatile__ ("sync"); 124 udelay(200); 125 126 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 127 __asm__ __volatile__ ("sync"); 128 return msize; 129 } 130 131 int checkboard(void) 132 { 133 puts("Board: Freescale MPC8323ERDB\n"); 134 return 0; 135 } 136 137 static struct pci_region pci_regions[] = { 138 { 139 bus_start: CONFIG_SYS_PCI1_MEM_BASE, 140 phys_start: CONFIG_SYS_PCI1_MEM_PHYS, 141 size: CONFIG_SYS_PCI1_MEM_SIZE, 142 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH 143 }, 144 { 145 bus_start: CONFIG_SYS_PCI1_MMIO_BASE, 146 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, 147 size: CONFIG_SYS_PCI1_MMIO_SIZE, 148 flags: PCI_REGION_MEM 149 }, 150 { 151 bus_start: CONFIG_SYS_PCI1_IO_BASE, 152 phys_start: CONFIG_SYS_PCI1_IO_PHYS, 153 size: CONFIG_SYS_PCI1_IO_SIZE, 154 flags: PCI_REGION_IO 155 } 156 }; 157 158 void pci_init_board(void) 159 { 160 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; 161 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; 162 volatile law83xx_t *pci_law = immr->sysconf.pcilaw; 163 struct pci_region *reg[] = { pci_regions }; 164 165 /* Enable all 3 PCI_CLK_OUTPUTs. */ 166 clk->occr |= 0xe0000000; 167 168 /* Configure PCI Local Access Windows */ 169 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; 170 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; 171 172 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; 173 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; 174 175 mpc83xx_pci_init(1, reg); 176 } 177 178 #if defined(CONFIG_OF_BOARD_SETUP) 179 int ft_board_setup(void *blob, bd_t *bd) 180 { 181 ft_cpu_setup(blob, bd); 182 #ifdef CONFIG_PCI 183 ft_pci_setup(blob, bd); 184 #endif 185 186 return 0; 187 } 188 #endif 189 190 #if defined(CONFIG_SYS_I2C_MAC_OFFSET) 191 int mac_read_from_eeprom(void) 192 { 193 uchar buf[28]; 194 char str[18]; 195 int i = 0; 196 unsigned int crc = 0; 197 unsigned char enetvar[32]; 198 199 /* Read MAC addresses from EEPROM */ 200 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) { 201 printf("\nEEPROM @ 0x%02x read FAILED!!!\n", 202 CONFIG_SYS_I2C_EEPROM_ADDR); 203 } else { 204 uint32_t crc_buf; 205 206 memcpy(&crc_buf, &buf[24], sizeof(uint32_t)); 207 208 if (crc32(crc, buf, 24) == crc_buf) { 209 printf("Reading MAC from EEPROM\n"); 210 for (i = 0; i < 4; i++) { 211 if (memcmp(&buf[i * 6], "\0\0\0\0\0\0", 6)) { 212 sprintf(str, 213 "%02X:%02X:%02X:%02X:%02X:%02X", 214 buf[i * 6], buf[i * 6 + 1], 215 buf[i * 6 + 2], buf[i * 6 + 3], 216 buf[i * 6 + 4], buf[i * 6 + 5]); 217 sprintf((char *)enetvar, 218 i ? "eth%daddr" : "ethaddr", i); 219 env_set((char *)enetvar, str); 220 } 221 } 222 } 223 } 224 return 0; 225 } 226 #endif /* CONFIG_I2C_MAC_OFFSET */ 227