1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * 4 * Michael Barkowski <michael.barkowski@freescale.com> 5 * Based on mpc832xmds file by Dave Liu <daveliu@freescale.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published 9 * by the Free Software Foundation. 10 */ 11 12 #include <common.h> 13 #include <ioports.h> 14 #include <mpc83xx.h> 15 #include <i2c.h> 16 #include <spd.h> 17 #include <miiphy.h> 18 #include <command.h> 19 #include <libfdt.h> 20 #if defined(CONFIG_PCI) 21 #include <pci.h> 22 #endif 23 #if defined(CONFIG_SPD_EEPROM) 24 #include <spd_sdram.h> 25 #else 26 #include <asm/mmu.h> 27 #endif 28 29 const qe_iop_conf_t qe_iop_conf_tab[] = { 30 /* UCC3 */ 31 {1, 0, 1, 0, 1}, /* TxD0 */ 32 {1, 1, 1, 0, 1}, /* TxD1 */ 33 {1, 2, 1, 0, 1}, /* TxD2 */ 34 {1, 3, 1, 0, 1}, /* TxD3 */ 35 {1, 9, 1, 0, 1}, /* TxER */ 36 {1, 12, 1, 0, 1}, /* TxEN */ 37 {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */ 38 39 {1, 4, 2, 0, 1}, /* RxD0 */ 40 {1, 5, 2, 0, 1}, /* RxD1 */ 41 {1, 6, 2, 0, 1}, /* RxD2 */ 42 {1, 7, 2, 0, 1}, /* RxD3 */ 43 {1, 8, 2, 0, 1}, /* RxER */ 44 {1, 10, 2, 0, 1}, /* RxDV */ 45 {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */ 46 {1, 11, 2, 0, 1}, /* COL */ 47 {1, 13, 2, 0, 1}, /* CRS */ 48 49 /* UCC2 */ 50 {0, 18, 1, 0, 1}, /* TxD0 */ 51 {0, 19, 1, 0, 1}, /* TxD1 */ 52 {0, 20, 1, 0, 1}, /* TxD2 */ 53 {0, 21, 1, 0, 1}, /* TxD3 */ 54 {0, 27, 1, 0, 1}, /* TxER */ 55 {0, 30, 1, 0, 1}, /* TxEN */ 56 {3, 23, 2, 0, 1}, /* TxCLK->CLK3 */ 57 58 {0, 22, 2, 0, 1}, /* RxD0 */ 59 {0, 23, 2, 0, 1}, /* RxD1 */ 60 {0, 24, 2, 0, 1}, /* RxD2 */ 61 {0, 25, 2, 0, 1}, /* RxD3 */ 62 {0, 26, 1, 0, 1}, /* RxER */ 63 {0, 28, 2, 0, 1}, /* Rx_DV */ 64 {3, 21, 2, 0, 1}, /* RxCLK->CLK16 */ 65 {0, 29, 2, 0, 1}, /* COL */ 66 {0, 31, 2, 0, 1}, /* CRS */ 67 68 {3, 4, 3, 0, 2}, /* MDIO */ 69 {3, 5, 1, 0, 2}, /* MDC */ 70 71 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ 72 }; 73 74 int board_early_init_f(void) 75 { 76 return 0; 77 } 78 79 int fixed_sdram(void); 80 81 long int initdram(int board_type) 82 { 83 volatile immap_t *im = (immap_t *) CFG_IMMR; 84 u32 msize = 0; 85 86 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) 87 return -1; 88 89 /* DDR SDRAM - Main SODIMM */ 90 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; 91 92 msize = fixed_sdram(); 93 94 /* return total bus SDRAM size(bytes) -- DDR */ 95 return (msize * 1024 * 1024); 96 } 97 98 /************************************************************************* 99 * fixed sdram init -- doesn't use serial presence detect. 100 ************************************************************************/ 101 int fixed_sdram(void) 102 { 103 volatile immap_t *im = (immap_t *) CFG_IMMR; 104 u32 msize = 0; 105 u32 ddr_size; 106 u32 ddr_size_log2; 107 108 msize = CFG_DDR_SIZE; 109 for (ddr_size = msize << 20, ddr_size_log2 = 0; 110 (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { 111 if (ddr_size & 1) { 112 return -1; 113 } 114 } 115 im->sysconf.ddrlaw[0].ar = 116 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); 117 im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; 118 im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; 119 im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; 120 im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; 121 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; 122 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; 123 im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; 124 im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; 125 im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; 126 im->ddr.sdram_mode = CFG_DDR_MODE; 127 im->ddr.sdram_mode2 = CFG_DDR_MODE2; 128 im->ddr.sdram_interval = CFG_DDR_INTERVAL; 129 __asm__ __volatile__ ("sync"); 130 udelay(200); 131 132 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 133 __asm__ __volatile__ ("sync"); 134 return msize; 135 } 136 137 int checkboard(void) 138 { 139 puts("Board: Freescale MPC8323ERDB\n"); 140 return 0; 141 } 142 143 static struct pci_region pci_regions[] = { 144 { 145 bus_start: CFG_PCI1_MEM_BASE, 146 phys_start: CFG_PCI1_MEM_PHYS, 147 size: CFG_PCI1_MEM_SIZE, 148 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH 149 }, 150 { 151 bus_start: CFG_PCI1_MMIO_BASE, 152 phys_start: CFG_PCI1_MMIO_PHYS, 153 size: CFG_PCI1_MMIO_SIZE, 154 flags: PCI_REGION_MEM 155 }, 156 { 157 bus_start: CFG_PCI1_IO_BASE, 158 phys_start: CFG_PCI1_IO_PHYS, 159 size: CFG_PCI1_IO_SIZE, 160 flags: PCI_REGION_IO 161 } 162 }; 163 164 void pci_init_board(void) 165 { 166 volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; 167 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; 168 volatile law83xx_t *pci_law = immr->sysconf.pcilaw; 169 struct pci_region *reg[] = { pci_regions }; 170 171 /* Enable all 3 PCI_CLK_OUTPUTs. */ 172 clk->occr |= 0xe0000000; 173 174 /* Configure PCI Local Access Windows */ 175 pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; 176 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; 177 178 pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; 179 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; 180 181 mpc83xx_pci_init(1, reg, 0); 182 } 183 184 #if defined(CONFIG_OF_BOARD_SETUP) 185 void ft_board_setup(void *blob, bd_t *bd) 186 { 187 ft_cpu_setup(blob, bd); 188 #ifdef CONFIG_PCI 189 ft_pci_setup(blob, bd); 190 #endif 191 } 192 #endif 193