1 /*
2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
3  *
4  * Michael Barkowski <michael.barkowski@freescale.com>
5  * Based on mpc832xmds file by Dave Liu <daveliu@freescale.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License version 2 as published
9  * by the Free Software Foundation.
10  */
11 
12 #include <common.h>
13 #include <ioports.h>
14 #include <mpc83xx.h>
15 #include <i2c.h>
16 #include <miiphy.h>
17 #include <command.h>
18 #include <libfdt.h>
19 #if defined(CONFIG_PCI)
20 #include <pci.h>
21 #endif
22 #include <asm/mmu.h>
23 
24 const qe_iop_conf_t qe_iop_conf_tab[] = {
25 	/* UCC3 */
26 	{1,  0, 1, 0, 1}, /* TxD0 */
27 	{1,  1, 1, 0, 1}, /* TxD1 */
28 	{1,  2, 1, 0, 1}, /* TxD2 */
29 	{1,  3, 1, 0, 1}, /* TxD3 */
30 	{1,  9, 1, 0, 1}, /* TxER */
31 	{1, 12, 1, 0, 1}, /* TxEN */
32 	{3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
33 
34 	{1,  4, 2, 0, 1}, /* RxD0 */
35 	{1,  5, 2, 0, 1}, /* RxD1 */
36 	{1,  6, 2, 0, 1}, /* RxD2 */
37 	{1,  7, 2, 0, 1}, /* RxD3 */
38 	{1,  8, 2, 0, 1}, /* RxER */
39 	{1, 10, 2, 0, 1}, /* RxDV */
40 	{0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
41 	{1, 11, 2, 0, 1}, /* COL */
42 	{1, 13, 2, 0, 1}, /* CRS */
43 
44 	/* UCC2 */
45 	{0, 18, 1, 0, 1}, /* TxD0 */
46 	{0, 19, 1, 0, 1}, /* TxD1 */
47 	{0, 20, 1, 0, 1}, /* TxD2 */
48 	{0, 21, 1, 0, 1}, /* TxD3 */
49 	{0, 27, 1, 0, 1}, /* TxER */
50 	{0, 30, 1, 0, 1}, /* TxEN */
51 	{3, 23, 2, 0, 1}, /* TxCLK->CLK3 */
52 
53 	{0, 22, 2, 0, 1}, /* RxD0 */
54 	{0, 23, 2, 0, 1}, /* RxD1 */
55 	{0, 24, 2, 0, 1}, /* RxD2 */
56 	{0, 25, 2, 0, 1}, /* RxD3 */
57 	{0, 26, 1, 0, 1}, /* RxER */
58 	{0, 28, 2, 0, 1}, /* Rx_DV */
59 	{3, 21, 2, 0, 1}, /* RxCLK->CLK16 */
60 	{0, 29, 2, 0, 1}, /* COL */
61 	{0, 31, 2, 0, 1}, /* CRS */
62 
63 	{3,  4, 3, 0, 2}, /* MDIO */
64 	{3,  5, 1, 0, 2}, /* MDC */
65 
66 	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
67 };
68 
69 int fixed_sdram(void);
70 
71 phys_size_t initdram(int board_type)
72 {
73 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
74 	u32 msize = 0;
75 
76 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
77 		return -1;
78 
79 	/* DDR SDRAM - Main SODIMM */
80 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
81 
82 	msize = fixed_sdram();
83 
84 	/* return total bus SDRAM size(bytes)  -- DDR */
85 	return (msize * 1024 * 1024);
86 }
87 
88 /*************************************************************************
89  *  fixed sdram init -- doesn't use serial presence detect.
90  ************************************************************************/
91 int fixed_sdram(void)
92 {
93 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
94 	u32 msize = 0;
95 	u32 ddr_size;
96 	u32 ddr_size_log2;
97 
98 	msize = CONFIG_SYS_DDR_SIZE;
99 	for (ddr_size = msize << 20, ddr_size_log2 = 0;
100 	     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
101 		if (ddr_size & 1) {
102 			return -1;
103 		}
104 	}
105 	im->sysconf.ddrlaw[0].ar =
106 	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
107 	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
108 	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
109 	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
110 	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
111 	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
112 	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
113 	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
114 	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
115 	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
116 	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
117 	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
118 	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
119 	__asm__ __volatile__ ("sync");
120 	udelay(200);
121 
122 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
123 	__asm__ __volatile__ ("sync");
124 	return msize;
125 }
126 
127 int checkboard(void)
128 {
129 	puts("Board: Freescale MPC8323ERDB\n");
130 	return 0;
131 }
132 
133 static struct pci_region pci_regions[] = {
134 	{
135 		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
136 		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
137 		size: CONFIG_SYS_PCI1_MEM_SIZE,
138 		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
139 	},
140 	{
141 		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
142 		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
143 		size: CONFIG_SYS_PCI1_MMIO_SIZE,
144 		flags: PCI_REGION_MEM
145 	},
146 	{
147 		bus_start: CONFIG_SYS_PCI1_IO_BASE,
148 		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
149 		size: CONFIG_SYS_PCI1_IO_SIZE,
150 		flags: PCI_REGION_IO
151 	}
152 };
153 
154 void pci_init_board(void)
155 {
156 	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
157 	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
158 	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
159 	struct pci_region *reg[] = { pci_regions };
160 
161 	/* Enable all 3 PCI_CLK_OUTPUTs. */
162 	clk->occr |= 0xe0000000;
163 
164 	/* Configure PCI Local Access Windows */
165 	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
166 	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
167 
168 	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
169 	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
170 
171 	mpc83xx_pci_init(1, reg);
172 }
173 
174 #if defined(CONFIG_OF_BOARD_SETUP)
175 void ft_board_setup(void *blob, bd_t *bd)
176 {
177 	ft_cpu_setup(blob, bd);
178 #ifdef CONFIG_PCI
179 	ft_pci_setup(blob, bd);
180 #endif
181 }
182 #endif
183 
184 #if defined(CONFIG_SYS_I2C_MAC_OFFSET)
185 int mac_read_from_eeprom(void)
186 {
187 	uchar buf[28];
188 	char str[18];
189 	int i = 0;
190 	unsigned int crc = 0;
191 	unsigned char enetvar[32];
192 
193 	/* Read MAC addresses from EEPROM */
194 	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) {
195 		printf("\nEEPROM @ 0x%02x read FAILED!!!\n",
196 		       CONFIG_SYS_I2C_EEPROM_ADDR);
197 	} else {
198 		if (crc32(crc, buf, 24) == *(unsigned int *)&buf[24]) {
199 			printf("Reading MAC from EEPROM\n");
200 			for (i = 0; i < 4; i++) {
201 				if (memcmp(&buf[i * 6], "\0\0\0\0\0\0", 6)) {
202 					sprintf(str,
203 						"%02X:%02X:%02X:%02X:%02X:%02X",
204 						buf[i * 6], buf[i * 6 + 1],
205 						buf[i * 6 + 2], buf[i * 6 + 3],
206 						buf[i * 6 + 4], buf[i * 6 + 5]);
207 					sprintf((char *)enetvar,
208 						i ? "eth%daddr" : "ethaddr", i);
209 					setenv((char *)enetvar, str);
210 				}
211 			}
212 		}
213 	}
214 	return 0;
215 }
216 #endif				/* CONFIG_I2C_MAC_OFFSET */
217