1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2007 Freescale Semiconductor, Inc.
4  *
5  * Authors: Nick.Spence@freescale.com
6  *          Wilson.Lo@freescale.com
7  *          scottwood@freescale.com
8  */
9 
10 #include <common.h>
11 #include <mpc83xx.h>
12 #include <spd_sdram.h>
13 
14 #include <asm/bitops.h>
15 #include <asm/io.h>
16 
17 #include <asm/processor.h>
18 
19 DECLARE_GLOBAL_DATA_PTR;
20 
21 static void resume_from_sleep(void)
22 {
23 	u32 magic = *(u32 *)0;
24 
25 	typedef void (*func_t)(void);
26 	func_t resume = *(func_t *)4;
27 
28 	if (magic == 0xf5153ae5)
29 		resume();
30 
31 	gd->flags &= ~GD_FLG_SILENT;
32 	puts("\nResume from sleep failed: bad magic word\n");
33 }
34 
35 /* Fixed sdram init -- doesn't use serial presence detect.
36  *
37  * This is useful for faster booting in configs where the RAM is unlikely
38  * to be changed, or for things like NAND booting where space is tight.
39  */
40 #ifndef CONFIG_SYS_RAMBOOT
41 static long fixed_sdram(void)
42 {
43 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
44 	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
45 	u32 msize_log2 = __ilog2(msize);
46 
47 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000;
48 	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
49 	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
50 
51 	/*
52 	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
53 	 * or the DDR2 controller may fail to initialize correctly.
54 	 */
55 	__udelay(50000);
56 
57 	im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
58 	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
59 
60 	/* Currently we use only one CS, so disable the other bank. */
61 	im->ddr.cs_config[1] = 0;
62 
63 	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
64 	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
65 	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
66 	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
67 	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
68 
69 	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
70 		im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI;
71 	else
72 		im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
73 
74 	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
75 	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
76 	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
77 
78 	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
79 	sync();
80 
81 	/* enable DDR controller */
82 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
83 	sync();
84 
85 	return msize;
86 }
87 #else
88 static long fixed_sdram(void)
89 {
90 	return CONFIG_SYS_DDR_SIZE * 1024 * 1024;
91 }
92 #endif /* CONFIG_SYS_RAMBOOT */
93 
94 int dram_init(void)
95 {
96 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
97 	u32 msize;
98 
99 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
100 		return -ENXIO;
101 
102 	/* DDR SDRAM */
103 	msize = fixed_sdram();
104 
105 	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
106 		resume_from_sleep();
107 
108 	/* set total bus SDRAM size(bytes)  -- DDR */
109 	gd->ram_size = msize;
110 
111 	return 0;
112 }
113