1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * 4 * Author: Scott Wood <scottwood@freescale.com> 5 * Dave Liu <daveliu@freescale.com> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <hwconfig.h> 28 #include <i2c.h> 29 #include <libfdt.h> 30 #include <fdt_support.h> 31 #include <pci.h> 32 #include <mpc83xx.h> 33 #include <netdev.h> 34 #include <asm/io.h> 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 int board_early_init_f(void) 39 { 40 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 41 42 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) 43 gd->flags |= GD_FLG_SILENT; 44 45 return 0; 46 } 47 48 static u8 read_board_info(void) 49 { 50 u8 val8; 51 i2c_set_bus_num(0); 52 53 if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0) 54 return val8; 55 else 56 return 0; 57 } 58 59 int checkboard(void) 60 { 61 static const char * const rev_str[] = { 62 "0.0", 63 "0.1", 64 "1.0", 65 "1.1", 66 "<unknown>", 67 }; 68 u8 info; 69 int i; 70 71 info = read_board_info(); 72 i = (!info) ? 4: info & 0x03; 73 74 printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]); 75 76 return 0; 77 } 78 79 static struct pci_region pci_regions[] = { 80 { 81 bus_start: CONFIG_SYS_PCI_MEM_BASE, 82 phys_start: CONFIG_SYS_PCI_MEM_PHYS, 83 size: CONFIG_SYS_PCI_MEM_SIZE, 84 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH 85 }, 86 { 87 bus_start: CONFIG_SYS_PCI_MMIO_BASE, 88 phys_start: CONFIG_SYS_PCI_MMIO_PHYS, 89 size: CONFIG_SYS_PCI_MMIO_SIZE, 90 flags: PCI_REGION_MEM 91 }, 92 { 93 bus_start: CONFIG_SYS_PCI_IO_BASE, 94 phys_start: CONFIG_SYS_PCI_IO_PHYS, 95 size: CONFIG_SYS_PCI_IO_SIZE, 96 flags: PCI_REGION_IO 97 } 98 }; 99 100 static struct pci_region pcie_regions_0[] = { 101 { 102 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, 103 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, 104 .size = CONFIG_SYS_PCIE1_MEM_SIZE, 105 .flags = PCI_REGION_MEM, 106 }, 107 { 108 .bus_start = CONFIG_SYS_PCIE1_IO_BASE, 109 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, 110 .size = CONFIG_SYS_PCIE1_IO_SIZE, 111 .flags = PCI_REGION_IO, 112 }, 113 }; 114 115 static struct pci_region pcie_regions_1[] = { 116 { 117 .bus_start = CONFIG_SYS_PCIE2_MEM_BASE, 118 .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS, 119 .size = CONFIG_SYS_PCIE2_MEM_SIZE, 120 .flags = PCI_REGION_MEM, 121 }, 122 { 123 .bus_start = CONFIG_SYS_PCIE2_IO_BASE, 124 .phys_start = CONFIG_SYS_PCIE2_IO_PHYS, 125 .size = CONFIG_SYS_PCIE2_IO_SIZE, 126 .flags = PCI_REGION_IO, 127 }, 128 }; 129 130 void pci_init_board(void) 131 { 132 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; 133 volatile sysconf83xx_t *sysconf = &immr->sysconf; 134 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; 135 volatile law83xx_t *pci_law = immr->sysconf.pcilaw; 136 volatile law83xx_t *pcie_law = sysconf->pcielaw; 137 struct pci_region *reg[] = { pci_regions }; 138 struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; 139 int warmboot; 140 141 /* Enable all 3 PCI_CLK_OUTPUTs. */ 142 clk->occr |= 0xe0000000; 143 144 /* 145 * Configure PCI Local Access Windows 146 */ 147 pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; 148 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; 149 150 pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; 151 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; 152 153 warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; 154 warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF; 155 156 mpc83xx_pci_init(1, reg, warmboot); 157 158 /* Configure the clock for PCIE controller */ 159 clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM, 160 SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1); 161 162 /* Deassert the resets in the control register */ 163 out_be32(&sysconf->pecr1, 0xE0008000); 164 out_be32(&sysconf->pecr2, 0xE0008000); 165 udelay(2000); 166 167 /* Configure PCI Express Local Access Windows */ 168 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); 169 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); 170 171 out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); 172 out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); 173 174 mpc83xx_pcie_init(2, pcie_reg, warmboot); 175 } 176 177 #if defined(CONFIG_OF_BOARD_SETUP) 178 void fdt_tsec1_fixup(void *fdt, bd_t *bd) 179 { 180 const char disabled[] = "disabled"; 181 const char *path; 182 int ret; 183 184 if (hwconfig_arg_cmp("board_type", "tsec1")) { 185 return; 186 } else if (!hwconfig_arg_cmp("board_type", "ulpi")) { 187 printf("NOTICE: No or unknown board_type hwconfig specified.\n" 188 " Assuming board with TSEC1.\n"); 189 return; 190 } 191 192 ret = fdt_path_offset(fdt, "/aliases"); 193 if (ret < 0) { 194 printf("WARNING: can't find /aliases node\n"); 195 return; 196 } 197 198 path = fdt_getprop(fdt, ret, "ethernet0", NULL); 199 if (!path) { 200 printf("WARNING: can't find ethernet0 alias\n"); 201 return; 202 } 203 204 do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1); 205 } 206 207 void ft_board_setup(void *blob, bd_t *bd) 208 { 209 ft_cpu_setup(blob, bd); 210 #ifdef CONFIG_PCI 211 ft_pci_setup(blob, bd); 212 #endif 213 fdt_fixup_dr_usb(blob, bd); 214 fdt_tsec1_fixup(blob, bd); 215 } 216 #endif 217 218 int board_eth_init(bd_t *bis) 219 { 220 cpu_eth_init(bis); /* Initialize TSECs first */ 221 return pci_eth_init(bis); 222 } 223