1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * 4 * Author: Scott Wood <scottwood@freescale.com> 5 * Dave Liu <daveliu@freescale.com> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <i2c.h> 28 #include <libfdt.h> 29 #include <fdt_support.h> 30 #include <pci.h> 31 #include <mpc83xx.h> 32 #include <netdev.h> 33 #include <asm/io.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 int board_early_init_f(void) 38 { 39 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 40 41 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) 42 gd->flags |= GD_FLG_SILENT; 43 44 return 0; 45 } 46 47 static u8 read_board_info(void) 48 { 49 u8 val8; 50 i2c_set_bus_num(0); 51 52 if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0) 53 return val8; 54 else 55 return 0; 56 } 57 58 int checkboard(void) 59 { 60 static const char * const rev_str[] = { 61 "0.0", 62 "0.1", 63 "1.0", 64 "1.1", 65 "<unknown>", 66 }; 67 u8 info; 68 int i; 69 70 info = read_board_info(); 71 i = (!info) ? 4: info & 0x03; 72 73 printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]); 74 75 return 0; 76 } 77 78 static struct pci_region pci_regions[] = { 79 { 80 bus_start: CONFIG_SYS_PCI_MEM_BASE, 81 phys_start: CONFIG_SYS_PCI_MEM_PHYS, 82 size: CONFIG_SYS_PCI_MEM_SIZE, 83 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH 84 }, 85 { 86 bus_start: CONFIG_SYS_PCI_MMIO_BASE, 87 phys_start: CONFIG_SYS_PCI_MMIO_PHYS, 88 size: CONFIG_SYS_PCI_MMIO_SIZE, 89 flags: PCI_REGION_MEM 90 }, 91 { 92 bus_start: CONFIG_SYS_PCI_IO_BASE, 93 phys_start: CONFIG_SYS_PCI_IO_PHYS, 94 size: CONFIG_SYS_PCI_IO_SIZE, 95 flags: PCI_REGION_IO 96 } 97 }; 98 99 static struct pci_region pcie_regions_0[] = { 100 { 101 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, 102 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, 103 .size = CONFIG_SYS_PCIE1_MEM_SIZE, 104 .flags = PCI_REGION_MEM, 105 }, 106 { 107 .bus_start = CONFIG_SYS_PCIE1_IO_BASE, 108 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, 109 .size = CONFIG_SYS_PCIE1_IO_SIZE, 110 .flags = PCI_REGION_IO, 111 }, 112 }; 113 114 static struct pci_region pcie_regions_1[] = { 115 { 116 .bus_start = CONFIG_SYS_PCIE2_MEM_BASE, 117 .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS, 118 .size = CONFIG_SYS_PCIE2_MEM_SIZE, 119 .flags = PCI_REGION_MEM, 120 }, 121 { 122 .bus_start = CONFIG_SYS_PCIE2_IO_BASE, 123 .phys_start = CONFIG_SYS_PCIE2_IO_PHYS, 124 .size = CONFIG_SYS_PCIE2_IO_SIZE, 125 .flags = PCI_REGION_IO, 126 }, 127 }; 128 129 void pci_init_board(void) 130 { 131 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; 132 volatile sysconf83xx_t *sysconf = &immr->sysconf; 133 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; 134 volatile law83xx_t *pci_law = immr->sysconf.pcilaw; 135 volatile law83xx_t *pcie_law = sysconf->pcielaw; 136 struct pci_region *reg[] = { pci_regions }; 137 struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; 138 int warmboot; 139 140 /* Enable all 3 PCI_CLK_OUTPUTs. */ 141 clk->occr |= 0xe0000000; 142 143 /* 144 * Configure PCI Local Access Windows 145 */ 146 pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; 147 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; 148 149 pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; 150 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; 151 152 warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; 153 warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF; 154 155 mpc83xx_pci_init(1, reg, warmboot); 156 157 /* Configure the clock for PCIE controller */ 158 clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM, 159 SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1); 160 161 /* Deassert the resets in the control register */ 162 out_be32(&sysconf->pecr1, 0xE0008000); 163 out_be32(&sysconf->pecr2, 0xE0008000); 164 udelay(2000); 165 166 /* Configure PCI Express Local Access Windows */ 167 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); 168 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); 169 170 out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); 171 out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); 172 173 mpc83xx_pcie_init(2, pcie_reg, warmboot); 174 } 175 176 #if defined(CONFIG_OF_BOARD_SETUP) 177 void fdt_tsec1_fixup(void *fdt, bd_t *bd) 178 { 179 char *mpc8315erdb = getenv("mpc8315erdb"); 180 const char disabled[] = "disabled"; 181 const char *path; 182 int ret; 183 184 if (!mpc8315erdb) 185 return; 186 187 if (!strcmp(mpc8315erdb, "tsec1")) { 188 return; 189 } else if (strcmp(mpc8315erdb, "ulpi")) { 190 printf("WARNING: wrong `mpc8315erdb' environment " 191 "variable specified: `%s'. Should be `ulpi' " 192 "or `tsec1'.\n", mpc8315erdb); 193 return; 194 } 195 196 ret = fdt_path_offset(fdt, "/aliases"); 197 if (ret < 0) { 198 printf("WARNING: can't find /aliases node\n"); 199 return; 200 } 201 202 path = fdt_getprop(fdt, ret, "ethernet0", NULL); 203 if (!path) { 204 printf("WARNING: can't find ethernet0 alias\n"); 205 return; 206 } 207 208 do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1); 209 } 210 211 void ft_board_setup(void *blob, bd_t *bd) 212 { 213 ft_cpu_setup(blob, bd); 214 #ifdef CONFIG_PCI 215 ft_pci_setup(blob, bd); 216 #endif 217 fdt_fixup_dr_usb(blob, bd); 218 fdt_tsec1_fixup(blob, bd); 219 } 220 #endif 221 222 int board_eth_init(bd_t *bis) 223 { 224 cpu_eth_init(bis); /* Initialize TSECs first */ 225 return pci_eth_init(bis); 226 } 227