1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 3 * 4 * Authors: Nick.Spence@freescale.com 5 * Wilson.Lo@freescale.com 6 * scottwood@freescale.com 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 #include <common.h> 28 #include <mpc83xx.h> 29 #include <spd_sdram.h> 30 31 #include <asm/bitops.h> 32 #include <asm/io.h> 33 34 #include <asm/processor.h> 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC 39 static void resume_from_sleep(void) 40 { 41 u32 magic = *(u32 *)0; 42 43 typedef void (*func_t)(void); 44 func_t resume = *(func_t *)4; 45 46 if (magic == 0xf5153ae5) 47 resume(); 48 49 gd->flags &= ~GD_FLG_SILENT; 50 puts("\nResume from sleep failed: bad magic word\n"); 51 } 52 #endif 53 54 /* Fixed sdram init -- doesn't use serial presence detect. 55 * 56 * This is useful for faster booting in configs where the RAM is unlikely 57 * to be changed, or for things like NAND booting where space is tight. 58 */ 59 static long fixed_sdram(void) 60 { 61 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; 62 63 #ifndef CONFIG_SYS_RAMBOOT 64 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; 65 u32 msize_log2 = __ilog2(msize); 66 67 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; 68 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); 69 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; 70 71 /* 72 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], 73 * or the DDR2 controller may fail to initialize correctly. 74 */ 75 __udelay(50000); 76 77 im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; 78 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG; 79 80 /* Currently we use only one CS, so disable the other bank. */ 81 im->ddr.cs_config[1] = 0; 82 83 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; 84 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 85 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 86 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 87 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 88 89 #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC 90 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) 91 im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI; 92 else 93 #endif 94 im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG; 95 96 im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2; 97 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; 98 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2; 99 100 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; 101 sync(); 102 103 /* enable DDR controller */ 104 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 105 #endif 106 107 return msize; 108 } 109 110 phys_size_t initdram(int board_type) 111 { 112 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; 113 volatile fsl_lbc_t *lbc = &im->im_lbc; 114 u32 msize; 115 116 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) 117 return -1; 118 119 /* DDR SDRAM - Main SODIMM */ 120 msize = fixed_sdram(); 121 122 /* Local Bus setup lbcr and mrtpr */ 123 lbc->lbcr = CONFIG_SYS_LBC_LBCR; 124 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; 125 sync(); 126 127 #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC 128 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) 129 resume_from_sleep(); 130 #endif 131 132 /* return total bus SDRAM size(bytes) -- DDR */ 133 return msize; 134 } 135