1 /*
2  * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
3  *
4  * Authors: Nick.Spence@freescale.com
5  *          Wilson.Lo@freescale.com
6  *          scottwood@freescale.com
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 
11 #include <common.h>
12 #include <mpc83xx.h>
13 #include <spd_sdram.h>
14 
15 #include <asm/bitops.h>
16 #include <asm/io.h>
17 
18 #include <asm/processor.h>
19 
20 DECLARE_GLOBAL_DATA_PTR;
21 
22 #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
23 static void resume_from_sleep(void)
24 {
25 	u32 magic = *(u32 *)0;
26 
27 	typedef void (*func_t)(void);
28 	func_t resume = *(func_t *)4;
29 
30 	if (magic == 0xf5153ae5)
31 		resume();
32 
33 	gd->flags &= ~GD_FLG_SILENT;
34 	puts("\nResume from sleep failed: bad magic word\n");
35 }
36 #endif
37 
38 /* Fixed sdram init -- doesn't use serial presence detect.
39  *
40  * This is useful for faster booting in configs where the RAM is unlikely
41  * to be changed, or for things like NAND booting where space is tight.
42  */
43 static long fixed_sdram(void)
44 {
45 	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
46 
47 #ifndef CONFIG_SYS_RAMBOOT
48 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
49 	u32 msize_log2 = __ilog2(msize);
50 
51 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
52 	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
53 	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
54 
55 	/*
56 	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
57 	 * or the DDR2 controller may fail to initialize correctly.
58 	 */
59 	__udelay(50000);
60 
61 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
62 #warning Chip select bounds is only configurable in 16MB increments
63 #endif
64 	im->ddr.csbnds[0].csbnds =
65 		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
66 		(((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
67 			CSBNDS_EA);
68 	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
69 
70 	/* Currently we use only one CS, so disable the other bank. */
71 	im->ddr.cs_config[1] = 0;
72 
73 	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
74 	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
75 	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
76 	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
77 	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
78 
79 #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
80 	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
81 		im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI;
82 	else
83 #endif
84 		im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG;
85 
86 	im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2;
87 	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
88 	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2;
89 
90 	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
91 	sync();
92 
93 	/* enable DDR controller */
94 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
95 #endif
96 
97 	return msize;
98 }
99 
100 phys_size_t initdram(int board_type)
101 {
102 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
103 	volatile fsl_lbc_t *lbc = &im->im_lbc;
104 	u32 msize;
105 
106 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
107 		return -1;
108 
109 	/* DDR SDRAM - Main SODIMM */
110 	msize = fixed_sdram();
111 
112 	/* Local Bus setup lbcr and mrtpr */
113 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
114 	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
115 	sync();
116 
117 #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
118 	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
119 		resume_from_sleep();
120 #endif
121 
122 	/* return total bus SDRAM size(bytes)  -- DDR */
123 	return msize;
124 }
125