1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2007 Freescale Semiconductor, Inc. 4 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 5 * 6 * Authors: Nick.Spence@freescale.com 7 * Wilson.Lo@freescale.com 8 * scottwood@freescale.com 9 * 10 * This files is mostly identical to the original from 11 * board\freescale\mpc8315erdb\sdram.c 12 */ 13 14 #include <common.h> 15 #include <mpc83xx.h> 16 17 #include <asm/bitops.h> 18 #include <asm/io.h> 19 20 #include <asm/processor.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 /* Fixed sdram init -- doesn't use serial presence detect. 25 * 26 * This is useful for faster booting in configs where the RAM is unlikely 27 * to be changed, or for things like NAND booting where space is tight. 28 */ 29 static long fixed_sdram(void) 30 { 31 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 32 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; 33 u32 msize_log2 = __ilog2(msize); 34 35 out_be32(&im->sysconf.ddrlaw[0].bar, 36 CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); 37 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); 38 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); 39 40 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); 41 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); 42 43 /* Currently we use only one CS, so disable the other bank. */ 44 out_be32(&im->ddr.cs_config[1], 0); 45 46 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); 47 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); 48 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); 49 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); 50 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); 51 52 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); 53 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); 54 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); 55 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); 56 57 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); 58 sync(); 59 60 /* enable DDR controller */ 61 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); 62 sync(); 63 64 return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); 65 } 66 67 int dram_init(void) 68 { 69 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 70 u32 msize; 71 72 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) 73 return -ENXIO; 74 75 /* DDR SDRAM */ 76 msize = fixed_sdram(); 77 78 /* return total bus SDRAM size(bytes) -- DDR */ 79 gd->ram_size = msize; 80 81 return 0; 82 } 83