1 /*
2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
3  * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
4  *
5  * Authors: Nick.Spence@freescale.com
6  *          Wilson.Lo@freescale.com
7  *          scottwood@freescale.com
8  *
9  * This files is  mostly identical to the original from
10  * board\freescale\mpc8315erdb\sdram.c
11  *
12  * See file CREDITS for list of people who contributed to this
13  * project.
14  *
15  * This program is free software; you can redistribute it and/or
16  * modify it under the terms of the GNU General Public License as
17  * published by the Free Software Foundation; either version 2 of
18  * the License, or (at your option) any later version.
19  *
20  * This program is distributed in the hope that it will be useful,
21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
22  * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
23  * GNU General Public License for more details.
24  *
25  * You should have received a copy of the GNU General Public License
26  * along with this program; if not, write to the Free Software
27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28  * MA 02111-1307 USA
29  */
30 
31 #include <common.h>
32 #include <mpc83xx.h>
33 
34 #include <asm/bitops.h>
35 #include <asm/io.h>
36 
37 #include <asm/processor.h>
38 
39 DECLARE_GLOBAL_DATA_PTR;
40 
41 static void resume_from_sleep(void)
42 {
43 	u32 magic = *(u32 *)0;
44 
45 	typedef void (*func_t)(void);
46 	func_t resume = *(func_t *)4;
47 
48 	if (magic == 0xf5153ae5)
49 		resume();
50 
51 	gd->flags &= ~GD_FLG_SILENT;
52 	puts("\nResume from sleep failed: bad magic word\n");
53 }
54 
55 /* Fixed sdram init -- doesn't use serial presence detect.
56  *
57  * This is useful for faster booting in configs where the RAM is unlikely
58  * to be changed, or for things like NAND booting where space is tight.
59  */
60 static long fixed_sdram(void)
61 {
62 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
63 	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
64 	u32 msize_log2 = __ilog2(msize);
65 
66 	out_be32(&im->sysconf.ddrlaw[0].bar,
67 			CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000);
68 	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
69 	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
70 
71 	/*
72 	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
73 	 * or the DDR2 controller may fail to initialize correctly.
74 	 */
75 	udelay(50000);
76 
77 	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
78 	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
79 
80 	/* Currently we use only one CS, so disable the other bank. */
81 	out_be32(&im->ddr.cs_config[1], 0);
82 
83 	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
84 	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
85 	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
86 	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
87 	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
88 
89 	if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF) {
90 		out_be32(&im->ddr.sdram_cfg,
91 			CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI);
92 	} else {
93 		out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
94 	}
95 
96 	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
97 	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
98 	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
99 
100 	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
101 	sync();
102 
103 	/* enable DDR controller */
104 	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
105 	sync();
106 
107 	return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
108 }
109 
110 phys_size_t initdram(int board_type)
111 {
112 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
113 	u32 msize;
114 
115 	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
116 		return -1;
117 
118 	/* DDR SDRAM */
119 	msize = fixed_sdram();
120 
121 	if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF)
122 		resume_from_sleep();
123 
124 	/* return total bus SDRAM size(bytes)  -- DDR */
125 	return msize;
126 }
127