1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 4 * 5 * Authors: Nick.Spence@freescale.com 6 * Wilson.Lo@freescale.com 7 * scottwood@freescale.com 8 * 9 * This files is mostly identical to the original from 10 * board\freescale\mpc8315erdb\sdram.c 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31 #include <common.h> 32 #include <mpc83xx.h> 33 34 #include <asm/bitops.h> 35 #include <asm/io.h> 36 37 #include <asm/processor.h> 38 39 DECLARE_GLOBAL_DATA_PTR; 40 41 /* Fixed sdram init -- doesn't use serial presence detect. 42 * 43 * This is useful for faster booting in configs where the RAM is unlikely 44 * to be changed, or for things like NAND booting where space is tight. 45 */ 46 static long fixed_sdram(void) 47 { 48 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 49 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; 50 u32 msize_log2 = __ilog2(msize); 51 52 out_be32(&im->sysconf.ddrlaw[0].bar, 53 CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); 54 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); 55 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); 56 57 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); 58 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); 59 60 /* Currently we use only one CS, so disable the other bank. */ 61 out_be32(&im->ddr.cs_config[1], 0); 62 63 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); 64 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); 65 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); 66 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); 67 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); 68 69 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); 70 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); 71 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); 72 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); 73 74 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); 75 sync(); 76 77 /* enable DDR controller */ 78 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); 79 sync(); 80 81 return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); 82 } 83 84 phys_size_t initdram(int board_type) 85 { 86 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 87 u32 msize; 88 89 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) 90 return -1; 91 92 /* DDR SDRAM */ 93 msize = fixed_sdram(); 94 95 /* return total bus SDRAM size(bytes) -- DDR */ 96 return msize; 97 } 98