1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Board-specific sbf ddr/sdram init.
4 *
5 * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
6 */
7
8 #include <config.h>
9
10.global sbf_dram_init
11.text
12
13sbf_dram_init:
14	/* Dram Initialization a1, a2, and d0 */
15	/* mscr sdram */
16	move.l	#0xFC0A4074, %a1
17	move.b	#(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
18	nop
19
20	/* SDRAM Chip 0 and 1 */
21	move.l	#0xFC0B8110, %a1
22	move.l	#0xFC0B8114, %a2
23
24	/* calculate the size */
25	move.l	#0x13, %d1
26	move.l	#(CONFIG_SYS_SDRAM_SIZE), %d2
27#ifdef CONFIG_SYS_SDRAM_BASE1
28	lsr.l	#1, %d2
29#endif
30
31dramsz_loop:
32	lsr.l	#1, %d2
33	add.l	#1, %d1
34	cmp.l	#1, %d2
35	bne	dramsz_loop
36#ifdef CONFIG_SYS_NAND_BOOT
37	beq	asm_nand_chk_status
38#endif
39	/* SDRAM Chip 0 and 1 */
40	move.l	#(CONFIG_SYS_SDRAM_BASE), (%a1)
41	or.l	%d1, (%a1)
42#ifdef CONFIG_SYS_SDRAM_BASE1
43	move.l	#(CONFIG_SYS_SDRAM_BASE1), (%a2)
44	or.l	%d1, (%a2)
45#endif
46	nop
47
48	/* dram cfg1 and cfg2 */
49	move.l	#0xFC0B8008, %a1
50	move.l	#(CONFIG_SYS_SDRAM_CFG1), (%a1)
51	nop
52	move.l	#0xFC0B800C, %a2
53	move.l	#(CONFIG_SYS_SDRAM_CFG2), (%a2)
54	nop
55
56	move.l	#0xFC0B8000, %a1	/* Mode */
57	move.l	#0xFC0B8004, %a2	/* Ctrl */
58
59	/* Issue PALL */
60	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
61	nop
62
63	/* Issue LEMR */
64	move.l	#(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
65	nop
66	move.l	#(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
67	nop
68
69	move.l	#1000, %d1
70	bsr	asm_delay
71
72	/* Issue PALL */
73	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
74	nop
75
76	/* Perform two refresh cycles */
77	move.l	#(CONFIG_SYS_SDRAM_CTRL + 4), %d0
78	nop
79	move.l	%d0, (%a2)
80	move.l	%d0, (%a2)
81	nop
82
83	move.l	#(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1)
84	nop
85
86	move.l	#500, %d1
87	bsr	asm_delay
88
89	move.l	#(CONFIG_SYS_SDRAM_CTRL), %d1
90	and.l	#0x7FFFFFFF, %d1
91
92	or.l	#0x10000C00, %d1
93
94	move.l	%d1, (%a2)
95	nop
96
97	move.l	#2000, %d1
98	bsr	asm_delay
99
100	rts
101