1/*
2 * Board-specific sbf ddr/sdram init.
3 *
4 * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
5 *
6 * SPDX-License-Identifier:	GPL-2.0+
7 */
8
9 #include <config.h>
10
11.global sbf_dram_init
12.text
13
14sbf_dram_init:
15	/* Dram Initialization a1, a2, and d0 */
16	/* mscr sdram */
17	move.l	#0xFC0A4074, %a1
18	move.b	#(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
19	nop
20
21	/* SDRAM Chip 0 and 1 */
22	move.l	#0xFC0B8110, %a1
23	move.l	#0xFC0B8114, %a2
24
25	/* calculate the size */
26	move.l	#0x13, %d1
27	move.l	#(CONFIG_SYS_SDRAM_SIZE), %d2
28#ifdef CONFIG_SYS_SDRAM_BASE1
29	lsr.l	#1, %d2
30#endif
31
32dramsz_loop:
33	lsr.l	#1, %d2
34	add.l	#1, %d1
35	cmp.l	#1, %d2
36	bne	dramsz_loop
37#ifdef CONFIG_SYS_NAND_BOOT
38	beq	asm_nand_chk_status
39#endif
40	/* SDRAM Chip 0 and 1 */
41	move.l	#(CONFIG_SYS_SDRAM_BASE), (%a1)
42	or.l	%d1, (%a1)
43#ifdef CONFIG_SYS_SDRAM_BASE1
44	move.l	#(CONFIG_SYS_SDRAM_BASE1), (%a2)
45	or.l	%d1, (%a2)
46#endif
47	nop
48
49	/* dram cfg1 and cfg2 */
50	move.l	#0xFC0B8008, %a1
51	move.l	#(CONFIG_SYS_SDRAM_CFG1), (%a1)
52	nop
53	move.l	#0xFC0B800C, %a2
54	move.l	#(CONFIG_SYS_SDRAM_CFG2), (%a2)
55	nop
56
57	move.l	#0xFC0B8000, %a1	/* Mode */
58	move.l	#0xFC0B8004, %a2	/* Ctrl */
59
60	/* Issue PALL */
61	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
62	nop
63
64	/* Issue LEMR */
65	move.l	#(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
66	nop
67	move.l	#(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
68	nop
69
70	move.l	#1000, %d1
71	bsr	asm_delay
72
73	/* Issue PALL */
74	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
75	nop
76
77	/* Perform two refresh cycles */
78	move.l	#(CONFIG_SYS_SDRAM_CTRL + 4), %d0
79	nop
80	move.l	%d0, (%a2)
81	move.l	%d0, (%a2)
82	nop
83
84	move.l	#(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1)
85	nop
86
87	move.l	#500, %d1
88	bsr	asm_delay
89
90	move.l	#(CONFIG_SYS_SDRAM_CTRL), %d1
91	and.l	#0x7FFFFFFF, %d1
92
93	or.l	#0x10000C00, %d1
94
95	move.l	%d1, (%a2)
96	nop
97
98	move.l	#2000, %d1
99	bsr	asm_delay
100
101	rts
102