1 /*
2  * (C) Copyright 2000-2003
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  *
5  * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7  *
8  * See file CREDITS for list of people who contributed to this
9  * project.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License as
13  * published by the Free Software Foundation; either version 2 of
14  * the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24  * MA 02111-1307 USA
25  */
26 
27 #include <common.h>
28 #include <pci.h>
29 #include <asm/immap.h>
30 #include <asm/io.h>
31 
32 DECLARE_GLOBAL_DATA_PTR;
33 
34 int checkboard(void)
35 {
36 	puts("Board: ");
37 	puts("Freescale M54455 EVB\n");
38 	return 0;
39 };
40 
41 phys_size_t initdram(int board_type)
42 {
43 	u32 dramsize;
44 #ifdef CONFIG_CF_SBF
45 	/*
46 	 * Serial Boot: The dram is already initialized in start.S
47 	 * only require to return DRAM size
48 	 */
49 	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
50 #else
51 	sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
52 	gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
53 	u32 i;
54 
55 	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
56 
57 	for (i = 0x13; i < 0x20; i++) {
58 		if (dramsize == (1 << i))
59 			break;
60 	}
61 	i--;
62 
63 	out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
64 
65 	out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
66 	out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 | i);
67 
68 	out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
69 	out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
70 
71 	/* Issue PALL */
72 	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
73 
74 	/* Issue LEMR */
75 	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD | 0x408);
76 	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x300);
77 
78 	udelay(500);
79 
80 	/* Issue PALL */
81 	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
82 
83 	/* Perform two refresh cycles */
84 	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
85 	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
86 
87 	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x200);
88 
89 	out_be32(&sdram->sdcr,
90 		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
91 
92 	udelay(100);
93 #endif
94 	return (dramsize << 1);
95 };
96 
97 int testdram(void)
98 {
99 	/* TODO: XXX XXX XXX */
100 	printf("DRAM test not implemented!\n");
101 
102 	return (0);
103 }
104 
105 #if defined(CONFIG_CMD_IDE)
106 #include <ata.h>
107 
108 int ide_preinit(void)
109 {
110 	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
111 	u32 tmp;
112 
113 	tmp = (in_8(&gpio->par_fec) & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
114 	setbits_8(&gpio->par_fec, tmp);
115 	tmp = ((in_be16(&gpio->par_feci2c) & 0xf0ff) |
116 		(GPIO_PAR_FECI2C_MDC1_ATA_DIOR | GPIO_PAR_FECI2C_MDIO1_ATA_DIOW));
117 	setbits_be16(&gpio->par_feci2c, tmp);
118 
119 	setbits_be16(&gpio->par_ata,
120 		GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
121 		GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 |
122 		GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
123 		GPIO_PAR_ATA_IORDY_IORDY);
124 	setbits_be16(&gpio->par_pci,
125 		GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
126 
127 	return (0);
128 }
129 
130 void ide_set_reset(int idereset)
131 {
132 	atac_t *ata = (atac_t *) MMAP_ATA;
133 	long period;
134 	/*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
135 	int piotms[5][9] = {
136 		{70, 165, 60, 30, 50, 5, 20, 0, 35},	/* PIO 0 */
137 		{50, 125, 45, 20, 35, 5, 15, 0, 35},	/* PIO 1 */
138 		{30, 100, 30, 15, 20, 5, 10, 0, 35},	/* PIO 2 */
139 		{30, 80, 30, 10, 20, 5, 10, 0, 35},	/* PIO 3 */
140 		{25, 70, 20, 10, 20, 5, 10, 0, 35}
141 	};			/* PIO 4 */
142 
143 	if (idereset) {
144 		/* control reset */
145 		out_8(&ata->cr, 0);
146 		udelay(10000);
147 	} else {
148 #define CALC_TIMING(t) (t + period - 1) / period
149 		period = 1000000000 / gd->bus_clk;	/* period in ns */
150 
151 		/*ata->ton = CALC_TIMING (180); */
152 		out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
153 		out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
154 		out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
155 		out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
156 		out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
157 		out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
158 		out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
159 
160 		/* IORDY enable */
161 		out_8(&ata->cr, 0x40);
162 		udelay(200000);
163 		/* IORDY enable */
164 		setbits_8(&ata->cr, 0x01);
165 	}
166 }
167 #endif
168 
169 #if defined(CONFIG_PCI)
170 /*
171  * Initialize PCI devices, report devices found.
172  */
173 static struct pci_controller hose;
174 extern void pci_mcf5445x_init(struct pci_controller *hose);
175 
176 void pci_init_board(void)
177 {
178 	pci_mcf5445x_init(&hose);
179 }
180 #endif				/* CONFIG_PCI */
181 
182 #if defined(CONFIG_FLASH_CFI_LEGACY)
183 #include <flash.h>
184 ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
185 {
186 	int sect[] = CONFIG_SYS_ATMEL_SECT;
187 	int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ;
188 	int i, j, k;
189 
190 	if (base != CONFIG_SYS_ATMEL_BASE)
191 		return 0;
192 
193 	info->flash_id          = 0x01000000;
194 	info->portwidth         = 1;
195 	info->chipwidth         = 1;
196 	info->buffer_size       = 1;
197 	info->erase_blk_tout    = 16384;
198 	info->write_tout        = 2;
199 	info->buffer_write_tout = 5;
200 	info->vendor            = 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */
201 	info->cmd_reset         = 0x00F0;
202 	info->interface         = FLASH_CFI_X8;
203 	info->legacy_unlock     = 0;
204 	info->manufacturer_id   = (u16) ATM_MANUFACT;
205 	info->device_id         = ATM_ID_LV040;
206 	info->device_id2        = 0;
207 
208 	info->ext_addr          = 0;
209 	info->cfi_version       = 0x3133;
210 	info->cfi_offset        = 0x0000;
211 	info->addr_unlock1      = 0x00000555;
212 	info->addr_unlock2      = 0x000002AA;
213 	info->name              = "CFI conformant";
214 
215 	info->size              = 0;
216 	info->sector_count      = CONFIG_SYS_ATMEL_TOTALSECT;
217 	info->start[0] = base;
218 	for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) {
219 		info->size += sect[i] * sectsz[i];
220 
221 		for (j = 0; j < sect[i]; j++, k++) {
222 			info->start[k + 1] = info->start[k] + sectsz[i];
223 			info->protect[k] = 0;
224 		}
225 	}
226 
227 	return 1;
228 }
229 #endif				/* CONFIG_SYS_FLASH_CFI */
230