1 /* 2 * (C) Copyright 2000-2003 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 #include <config.h> 28 #include <common.h> 29 #include <asm/io.h> 30 #include <asm/immap.h> 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 #if defined(CONFIG_CMD_NAND) 35 #include <nand.h> 36 #include <linux/mtd/mtd.h> 37 38 #define SET_CLE 0x10 39 #define SET_ALE 0x08 40 41 static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) 42 { 43 struct nand_chip *this = mtdinfo->priv; 44 volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR; 45 46 if (ctrl & NAND_CTRL_CHANGE) { 47 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; 48 49 IO_ADDR_W &= ~(SET_ALE | SET_CLE); 50 51 if (ctrl & NAND_NCE) 52 *nCE &= 0xFFFB; 53 else 54 *nCE |= 0x0004; 55 56 if (ctrl & NAND_CLE) 57 IO_ADDR_W |= SET_CLE; 58 if (ctrl & NAND_ALE) 59 IO_ADDR_W |= SET_ALE; 60 61 this->IO_ADDR_W = (void *)IO_ADDR_W; 62 63 } 64 65 if (cmd != NAND_CMD_NONE) 66 writeb(cmd, this->IO_ADDR_W); 67 } 68 69 int board_nand_init(struct nand_chip *nand) 70 { 71 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 72 fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; 73 74 clrbits_be32(&fbcs->csmr2, FBCS_CSMR_WP); 75 76 /* 77 * set up pin configuration - enabled 2nd output buffer's signals 78 * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc) 79 * to use nCE signal 80 */ 81 clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3); 82 setbits_8(&gpio->pddr_timer, 0x08); 83 setbits_8(&gpio->ppd_timer, 0x08); 84 out_8(&gpio->pclrr_timer, 0); 85 out_8(&gpio->podr_timer, 0); 86 87 nand->chip_delay = 60; 88 nand->ecc.mode = NAND_ECC_SOFT; 89 nand->cmd_ctrl = nand_hwcontrol; 90 91 return 0; 92 } 93 #endif 94