1 /* 2 * (C) Copyright 2000-2003 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 #include <config.h> 28 #include <common.h> 29 #include <asm/io.h> 30 #include <asm/immap.h> 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 #if defined(CONFIG_CMD_NAND) 35 #include <nand.h> 36 #include <linux/mtd/mtd.h> 37 38 #define SET_CLE 0x10 39 #define SET_ALE 0x08 40 41 static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) 42 { 43 struct nand_chip *this = mtdinfo->priv; 44 volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; 45 u32 nand_baseaddr = (u32) this->IO_ADDR_W; 46 47 if (ctrl & NAND_CTRL_CHANGE) { 48 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; 49 IO_ADDR_W &= ~(SET_ALE | SE_CLE); 50 51 if (ctrl & NAND_CLE) 52 IO_ADDR_W |= SET_CLE; 53 if (ctrl & NAND_ALE) 54 IO_ADDR_W |= SET_ALE; 55 56 at91_set_gpio_value(AT91_PIN_PD15, !(ctrl & NAND_NCE)); 57 this->IO_ADDR_W = (void *)IO_ADDR_W; 58 59 } 60 61 if (cmd != NAND_CMD_NONE) 62 writeb(cmd, this->IO_ADDR_W); 63 } 64 65 int board_nand_init(struct nand_chip *nand) 66 { 67 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; 68 volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; 69 70 *((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004; 71 fbcs->csmr2 &= ~FBCS_CSMR_WP; 72 73 /* set up pin configuration */ 74 gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3; 75 gpio->pddr_timer |= 0x08; 76 gpio->ppd_timer |= 0x08; 77 gpio->pclrr_timer = 0; 78 gpio->podr_timer = 0; 79 80 nand->chip_delay = 50; 81 nand->ecc.mode = NAND_ECC_SOFT; 82 nand->cmd_ctrl = nand_hwcontrol; 83 84 return 0; 85 } 86 #endif 87