1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 21ac559d4STsiChungLiew /* 31ac559d4STsiChungLiew * (C) Copyright 2000-2003 41ac559d4STsiChungLiew * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 51ac559d4STsiChungLiew * 6aa0d99fcSAlison Wang * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 71ac559d4STsiChungLiew * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 81ac559d4STsiChungLiew */ 91ac559d4STsiChungLiew 101ac559d4STsiChungLiew #include <config.h> 111ac559d4STsiChungLiew #include <common.h> 121ac559d4STsiChungLiew #include <asm/io.h> 131ac559d4STsiChungLiew #include <asm/immap.h> 141ac559d4STsiChungLiew 151ac559d4STsiChungLiew #if defined(CONFIG_CMD_NAND) 161ac559d4STsiChungLiew #include <nand.h> 171ac559d4STsiChungLiew #include <linux/mtd/mtd.h> 181ac559d4STsiChungLiew 191ac559d4STsiChungLiew #define SET_CLE 0x10 201ac559d4STsiChungLiew #define SET_ALE 0x08 211ac559d4STsiChungLiew 22f64cb652SScott Wood static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) 231ac559d4STsiChungLiew { 2417cb4b8fSScott Wood struct nand_chip *this = mtd_to_nand(mtdinfo); 25e4f69d1bSTsiChung Liew volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR; 261ac559d4STsiChungLiew 27f64cb652SScott Wood if (ctrl & NAND_CTRL_CHANGE) { 28f64cb652SScott Wood ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; 29f64cb652SScott Wood 30e4f69d1bSTsiChung Liew IO_ADDR_W &= ~(SET_ALE | SET_CLE); 31e4f69d1bSTsiChung Liew 32e4f69d1bSTsiChung Liew if (ctrl & NAND_NCE) 339017d932STsiChung Liew *nCE &= 0xFFFB; 349017d932STsiChung Liew else 35e4f69d1bSTsiChung Liew *nCE |= 0x0004; 369017d932STsiChung Liew 37f64cb652SScott Wood if (ctrl & NAND_CLE) 38f64cb652SScott Wood IO_ADDR_W |= SET_CLE; 39f64cb652SScott Wood if (ctrl & NAND_ALE) 40f64cb652SScott Wood IO_ADDR_W |= SET_ALE; 41f64cb652SScott Wood 42f64cb652SScott Wood this->IO_ADDR_W = (void *)IO_ADDR_W; 43f64cb652SScott Wood 441ac559d4STsiChungLiew } 451ac559d4STsiChungLiew 46f64cb652SScott Wood if (cmd != NAND_CMD_NONE) 47f64cb652SScott Wood writeb(cmd, this->IO_ADDR_W); 481ac559d4STsiChungLiew } 491ac559d4STsiChungLiew 501ac559d4STsiChungLiew int board_nand_init(struct nand_chip *nand) 511ac559d4STsiChungLiew { 52aa0d99fcSAlison Wang gpio_t *gpio = (gpio_t *) MMAP_GPIO; 53aa0d99fcSAlison Wang fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; 541ac559d4STsiChungLiew 55aa0d99fcSAlison Wang clrbits_be32(&fbcs->csmr2, FBCS_CSMR_WP); 561ac559d4STsiChungLiew 57e4f69d1bSTsiChung Liew /* 58e4f69d1bSTsiChung Liew * set up pin configuration - enabled 2nd output buffer's signals 59e4f69d1bSTsiChung Liew * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc) 60e4f69d1bSTsiChung Liew * to use nCE signal 61e4f69d1bSTsiChung Liew */ 62aa0d99fcSAlison Wang clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3); 63aa0d99fcSAlison Wang setbits_8(&gpio->pddr_timer, 0x08); 64aa0d99fcSAlison Wang setbits_8(&gpio->ppd_timer, 0x08); 65aa0d99fcSAlison Wang out_8(&gpio->pclrr_timer, 0); 66aa0d99fcSAlison Wang out_8(&gpio->podr_timer, 0); 671ac559d4STsiChungLiew 689017d932STsiChung Liew nand->chip_delay = 60; 69f64cb652SScott Wood nand->ecc.mode = NAND_ECC_SOFT; 70f64cb652SScott Wood nand->cmd_ctrl = nand_hwcontrol; 711ac559d4STsiChungLiew 721ac559d4STsiChungLiew return 0; 731ac559d4STsiChungLiew } 741ac559d4STsiChungLiew #endif 75