1*1ac559d4STsiChungLiew /* 2*1ac559d4STsiChungLiew * (C) Copyright 2000-2003 3*1ac559d4STsiChungLiew * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4*1ac559d4STsiChungLiew * 5*1ac559d4STsiChungLiew * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 6*1ac559d4STsiChungLiew * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7*1ac559d4STsiChungLiew * 8*1ac559d4STsiChungLiew * See file CREDITS for list of people who contributed to this 9*1ac559d4STsiChungLiew * project. 10*1ac559d4STsiChungLiew * 11*1ac559d4STsiChungLiew * This program is free software; you can redistribute it and/or 12*1ac559d4STsiChungLiew * modify it under the terms of the GNU General Public License as 13*1ac559d4STsiChungLiew * published by the Free Software Foundation; either version 2 of 14*1ac559d4STsiChungLiew * the License, or (at your option) any later version. 15*1ac559d4STsiChungLiew * 16*1ac559d4STsiChungLiew * This program is distributed in the hope that it will be useful, 17*1ac559d4STsiChungLiew * but WITHOUT ANY WARRANTY; without even the implied warranty of 18*1ac559d4STsiChungLiew * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19*1ac559d4STsiChungLiew * GNU General Public License for more details. 20*1ac559d4STsiChungLiew * 21*1ac559d4STsiChungLiew * You should have received a copy of the GNU General Public License 22*1ac559d4STsiChungLiew * along with this program; if not, write to the Free Software 23*1ac559d4STsiChungLiew * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24*1ac559d4STsiChungLiew * MA 02111-1307 USA 25*1ac559d4STsiChungLiew */ 26*1ac559d4STsiChungLiew 27*1ac559d4STsiChungLiew #include <config.h> 28*1ac559d4STsiChungLiew #include <common.h> 29*1ac559d4STsiChungLiew #include <asm/io.h> 30*1ac559d4STsiChungLiew #include <asm/immap.h> 31*1ac559d4STsiChungLiew 32*1ac559d4STsiChungLiew DECLARE_GLOBAL_DATA_PTR; 33*1ac559d4STsiChungLiew 34*1ac559d4STsiChungLiew #if defined(CONFIG_CMD_NAND) 35*1ac559d4STsiChungLiew #include <nand.h> 36*1ac559d4STsiChungLiew #include <linux/mtd/mtd.h> 37*1ac559d4STsiChungLiew 38*1ac559d4STsiChungLiew #define SET_CLE 0x10 39*1ac559d4STsiChungLiew #define CLR_CLE ~SET_CLE 40*1ac559d4STsiChungLiew #define SET_ALE 0x08 41*1ac559d4STsiChungLiew #define CLR_ALE ~SET_ALE 42*1ac559d4STsiChungLiew 43*1ac559d4STsiChungLiew static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd) 44*1ac559d4STsiChungLiew { 45*1ac559d4STsiChungLiew struct nand_chip *this = mtdinfo->priv; 46*1ac559d4STsiChungLiew volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; 47*1ac559d4STsiChungLiew u32 nand_baseaddr = (u32) this->IO_ADDR_W; 48*1ac559d4STsiChungLiew 49*1ac559d4STsiChungLiew switch (cmd) { 50*1ac559d4STsiChungLiew case NAND_CTL_SETNCE: 51*1ac559d4STsiChungLiew case NAND_CTL_CLRNCE: 52*1ac559d4STsiChungLiew break; 53*1ac559d4STsiChungLiew case NAND_CTL_SETCLE: 54*1ac559d4STsiChungLiew nand_baseaddr |= SET_CLE; 55*1ac559d4STsiChungLiew break; 56*1ac559d4STsiChungLiew case NAND_CTL_CLRCLE: 57*1ac559d4STsiChungLiew nand_baseaddr &= CLR_CLE; 58*1ac559d4STsiChungLiew break; 59*1ac559d4STsiChungLiew case NAND_CTL_SETALE: 60*1ac559d4STsiChungLiew nand_baseaddr |= SET_ALE; 61*1ac559d4STsiChungLiew break; 62*1ac559d4STsiChungLiew case NAND_CTL_CLRALE: 63*1ac559d4STsiChungLiew nand_baseaddr |= CLR_ALE; 64*1ac559d4STsiChungLiew break; 65*1ac559d4STsiChungLiew case NAND_CTL_SETWP: 66*1ac559d4STsiChungLiew fbcs->csmr2 |= FBCS_CSMR_WP; 67*1ac559d4STsiChungLiew break; 68*1ac559d4STsiChungLiew case NAND_CTL_CLRWP: 69*1ac559d4STsiChungLiew fbcs->csmr2 &= ~FBCS_CSMR_WP; 70*1ac559d4STsiChungLiew break; 71*1ac559d4STsiChungLiew } 72*1ac559d4STsiChungLiew this->IO_ADDR_W = (void __iomem *)(nand_baseaddr); 73*1ac559d4STsiChungLiew } 74*1ac559d4STsiChungLiew 75*1ac559d4STsiChungLiew static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte) 76*1ac559d4STsiChungLiew { 77*1ac559d4STsiChungLiew struct nand_chip *this = mtdinfo->priv; 78*1ac559d4STsiChungLiew *((volatile u8 *)(this->IO_ADDR_W)) = byte; 79*1ac559d4STsiChungLiew } 80*1ac559d4STsiChungLiew 81*1ac559d4STsiChungLiew static u8 nand_read_byte(struct mtd_info *mtdinfo) 82*1ac559d4STsiChungLiew { 83*1ac559d4STsiChungLiew struct nand_chip *this = mtdinfo->priv; 84*1ac559d4STsiChungLiew return (u8) (*((volatile u8 *)this->IO_ADDR_R)); 85*1ac559d4STsiChungLiew } 86*1ac559d4STsiChungLiew 87*1ac559d4STsiChungLiew static int nand_dev_ready(struct mtd_info *mtdinfo) 88*1ac559d4STsiChungLiew { 89*1ac559d4STsiChungLiew return 1; 90*1ac559d4STsiChungLiew } 91*1ac559d4STsiChungLiew 92*1ac559d4STsiChungLiew int board_nand_init(struct nand_chip *nand) 93*1ac559d4STsiChungLiew { 94*1ac559d4STsiChungLiew volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; 95*1ac559d4STsiChungLiew 96*1ac559d4STsiChungLiew *((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004; 97*1ac559d4STsiChungLiew 98*1ac559d4STsiChungLiew /* set up pin configuration */ 99*1ac559d4STsiChungLiew gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3; 100*1ac559d4STsiChungLiew gpio->pddr_timer |= 0x08; 101*1ac559d4STsiChungLiew gpio->ppd_timer |= 0x08; 102*1ac559d4STsiChungLiew gpio->pclrr_timer = 0; 103*1ac559d4STsiChungLiew gpio->podr_timer = 0; 104*1ac559d4STsiChungLiew 105*1ac559d4STsiChungLiew nand->chip_delay = 50; 106*1ac559d4STsiChungLiew nand->eccmode = NAND_ECC_SOFT; 107*1ac559d4STsiChungLiew nand->hwcontrol = nand_hwcontrol; 108*1ac559d4STsiChungLiew nand->read_byte = nand_read_byte; 109*1ac559d4STsiChungLiew nand->write_byte = nand_write_byte; 110*1ac559d4STsiChungLiew nand->dev_ready = nand_dev_ready; 111*1ac559d4STsiChungLiew 112*1ac559d4STsiChungLiew return 0; 113*1ac559d4STsiChungLiew } 114*1ac559d4STsiChungLiew #endif 115