1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2000-2003 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 8 */ 9 10 #include <config.h> 11 #include <common.h> 12 #include <asm/io.h> 13 #include <asm/immap.h> 14 15 #if defined(CONFIG_CMD_NAND) 16 #include <nand.h> 17 #include <linux/mtd/mtd.h> 18 19 #define SET_CLE 0x10 20 #define SET_ALE 0x08 21 22 static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) 23 { 24 struct nand_chip *this = mtd_to_nand(mtdinfo); 25 volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR; 26 27 if (ctrl & NAND_CTRL_CHANGE) { 28 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; 29 30 IO_ADDR_W &= ~(SET_ALE | SET_CLE); 31 32 if (ctrl & NAND_NCE) 33 *nCE &= 0xFFFB; 34 else 35 *nCE |= 0x0004; 36 37 if (ctrl & NAND_CLE) 38 IO_ADDR_W |= SET_CLE; 39 if (ctrl & NAND_ALE) 40 IO_ADDR_W |= SET_ALE; 41 42 this->IO_ADDR_W = (void *)IO_ADDR_W; 43 } 44 45 if (cmd != NAND_CMD_NONE) 46 writeb(cmd, this->IO_ADDR_W); 47 } 48 49 int board_nand_init(struct nand_chip *nand) 50 { 51 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 52 53 /* 54 * set up pin configuration - enabled 2nd output buffer's signals 55 * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc) 56 * to use nCE signal 57 */ 58 clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3); 59 setbits_8(&gpio->pddr_timer, 0x08); 60 setbits_8(&gpio->ppd_timer, 0x08); 61 out_8(&gpio->pclrr_timer, 0); 62 out_8(&gpio->podr_timer, 0); 63 64 nand->chip_delay = 60; 65 nand->ecc.mode = NAND_ECC_SOFT; 66 nand->cmd_ctrl = nand_hwcontrol; 67 68 return 0; 69 } 70 #endif 71