1 /* 2 * (C) Copyright 2000-2003 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <config.h> 12 #include <common.h> 13 #include <asm/io.h> 14 #include <asm/immap.h> 15 16 #if defined(CONFIG_CMD_NAND) 17 #include <nand.h> 18 #include <linux/mtd/mtd.h> 19 20 #define SET_CLE 0x10 21 #define SET_ALE 0x08 22 23 static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) 24 { 25 struct nand_chip *this = mtd_to_nand(mtdinfo); 26 volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR; 27 28 if (ctrl & NAND_CTRL_CHANGE) { 29 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; 30 31 IO_ADDR_W &= ~(SET_ALE | SET_CLE); 32 33 if (ctrl & NAND_NCE) 34 *nCE &= 0xFFFB; 35 else 36 *nCE |= 0x0004; 37 38 if (ctrl & NAND_CLE) 39 IO_ADDR_W |= SET_CLE; 40 if (ctrl & NAND_ALE) 41 IO_ADDR_W |= SET_ALE; 42 43 this->IO_ADDR_W = (void *)IO_ADDR_W; 44 } 45 46 if (cmd != NAND_CMD_NONE) 47 writeb(cmd, this->IO_ADDR_W); 48 } 49 50 int board_nand_init(struct nand_chip *nand) 51 { 52 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 53 54 /* 55 * set up pin configuration - enabled 2nd output buffer's signals 56 * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc) 57 * to use nCE signal 58 */ 59 clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3); 60 setbits_8(&gpio->pddr_timer, 0x08); 61 setbits_8(&gpio->ppd_timer, 0x08); 62 out_8(&gpio->pclrr_timer, 0); 63 out_8(&gpio->podr_timer, 0); 64 65 nand->chip_delay = 60; 66 nand->ecc.mode = NAND_ECC_SOFT; 67 nand->cmd_ctrl = nand_hwcontrol; 68 69 return 0; 70 } 71 #endif 72