1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 21a33ce65STsiChungLiew /* 31a33ce65STsiChungLiew * (C) Copyright 2000-2003 41a33ce65STsiChungLiew * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 51a33ce65STsiChungLiew * 6aa0d99fcSAlison Wang * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 71a33ce65STsiChungLiew * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 81a33ce65STsiChungLiew */ 91a33ce65STsiChungLiew 101a33ce65STsiChungLiew #include <config.h> 111a33ce65STsiChungLiew #include <common.h> 121a33ce65STsiChungLiew #include <asm/io.h> 131a33ce65STsiChungLiew #include <asm/immap.h> 141a33ce65STsiChungLiew 15ab77bc54STsiChungLiew #if defined(CONFIG_CMD_NAND) 161a33ce65STsiChungLiew #include <nand.h> 171a33ce65STsiChungLiew #include <linux/mtd/mtd.h> 181a33ce65STsiChungLiew 191a33ce65STsiChungLiew #define SET_CLE 0x10 201a33ce65STsiChungLiew #define SET_ALE 0x08 211a33ce65STsiChungLiew 22e4f69d1bSTsiChung Liew static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) 231a33ce65STsiChungLiew { 2417cb4b8fSScott Wood struct nand_chip *this = mtd_to_nand(mtdinfo); 25e4f69d1bSTsiChung Liew volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR; 261a33ce65STsiChungLiew 27cfa460adSWilliam Juul if (ctrl & NAND_CTRL_CHANGE) { 28e4f69d1bSTsiChung Liew ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; 29e4f69d1bSTsiChung Liew 30e4f69d1bSTsiChung Liew IO_ADDR_W &= ~(SET_ALE | SET_CLE); 31e4f69d1bSTsiChung Liew 32e4f69d1bSTsiChung Liew if (ctrl & NAND_NCE) 339017d932STsiChung Liew *nCE &= 0xFFFB; 349017d932STsiChung Liew else 35e4f69d1bSTsiChung Liew *nCE |= 0x0004; 369017d932STsiChung Liew 37cfa460adSWilliam Juul if (ctrl & NAND_CLE) 38e4f69d1bSTsiChung Liew IO_ADDR_W |= SET_CLE; 39cfa460adSWilliam Juul if (ctrl & NAND_ALE) 40e4f69d1bSTsiChung Liew IO_ADDR_W |= SET_ALE; 41e4f69d1bSTsiChung Liew 42e4f69d1bSTsiChung Liew this->IO_ADDR_W = (void *)IO_ADDR_W; 431a33ce65STsiChungLiew } 44cfa460adSWilliam Juul 45cfa460adSWilliam Juul if (cmd != NAND_CMD_NONE) 46cfa460adSWilliam Juul writeb(cmd, this->IO_ADDR_W); 471a33ce65STsiChungLiew } 481a33ce65STsiChungLiew 491a33ce65STsiChungLiew int board_nand_init(struct nand_chip *nand) 501a33ce65STsiChungLiew { 51aa0d99fcSAlison Wang gpio_t *gpio = (gpio_t *) MMAP_GPIO; 521a33ce65STsiChungLiew 53e4f69d1bSTsiChung Liew /* 54e4f69d1bSTsiChung Liew * set up pin configuration - enabled 2nd output buffer's signals 55e4f69d1bSTsiChung Liew * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc) 56e4f69d1bSTsiChung Liew * to use nCE signal 57e4f69d1bSTsiChung Liew */ 58aa0d99fcSAlison Wang clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3); 59aa0d99fcSAlison Wang setbits_8(&gpio->pddr_timer, 0x08); 60aa0d99fcSAlison Wang setbits_8(&gpio->ppd_timer, 0x08); 61aa0d99fcSAlison Wang out_8(&gpio->pclrr_timer, 0); 62aa0d99fcSAlison Wang out_8(&gpio->podr_timer, 0); 631a33ce65STsiChungLiew 649017d932STsiChung Liew nand->chip_delay = 60; 65cfa460adSWilliam Juul nand->ecc.mode = NAND_ECC_SOFT; 66cfa460adSWilliam Juul nand->cmd_ctrl = nand_hwcontrol; 671a33ce65STsiChungLiew 681a33ce65STsiChungLiew return 0; 691a33ce65STsiChungLiew } 701a33ce65STsiChungLiew #endif 71