11a33ce65STsiChungLiew /* 21a33ce65STsiChungLiew * (C) Copyright 2000-2003 31a33ce65STsiChungLiew * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 41a33ce65STsiChungLiew * 5aa0d99fcSAlison Wang * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 61a33ce65STsiChungLiew * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 71a33ce65STsiChungLiew * 8*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 91a33ce65STsiChungLiew */ 101a33ce65STsiChungLiew 111a33ce65STsiChungLiew #include <config.h> 121a33ce65STsiChungLiew #include <common.h> 131a33ce65STsiChungLiew #include <asm/io.h> 141a33ce65STsiChungLiew #include <asm/immap.h> 151a33ce65STsiChungLiew 161a33ce65STsiChungLiew DECLARE_GLOBAL_DATA_PTR; 171a33ce65STsiChungLiew 18ab77bc54STsiChungLiew #if defined(CONFIG_CMD_NAND) 191a33ce65STsiChungLiew #include <nand.h> 201a33ce65STsiChungLiew #include <linux/mtd/mtd.h> 211a33ce65STsiChungLiew 221a33ce65STsiChungLiew #define SET_CLE 0x10 231a33ce65STsiChungLiew #define SET_ALE 0x08 241a33ce65STsiChungLiew 25e4f69d1bSTsiChung Liew static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) 261a33ce65STsiChungLiew { 271a33ce65STsiChungLiew struct nand_chip *this = mtdinfo->priv; 28e4f69d1bSTsiChung Liew volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR; 291a33ce65STsiChungLiew 30cfa460adSWilliam Juul if (ctrl & NAND_CTRL_CHANGE) { 31e4f69d1bSTsiChung Liew ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; 32e4f69d1bSTsiChung Liew 33e4f69d1bSTsiChung Liew IO_ADDR_W &= ~(SET_ALE | SET_CLE); 34e4f69d1bSTsiChung Liew 35e4f69d1bSTsiChung Liew if (ctrl & NAND_NCE) 369017d932STsiChung Liew *nCE &= 0xFFFB; 379017d932STsiChung Liew else 38e4f69d1bSTsiChung Liew *nCE |= 0x0004; 399017d932STsiChung Liew 40cfa460adSWilliam Juul if (ctrl & NAND_CLE) 41e4f69d1bSTsiChung Liew IO_ADDR_W |= SET_CLE; 42cfa460adSWilliam Juul if (ctrl & NAND_ALE) 43e4f69d1bSTsiChung Liew IO_ADDR_W |= SET_ALE; 44e4f69d1bSTsiChung Liew 45e4f69d1bSTsiChung Liew this->IO_ADDR_W = (void *)IO_ADDR_W; 461a33ce65STsiChungLiew } 47cfa460adSWilliam Juul 48cfa460adSWilliam Juul if (cmd != NAND_CMD_NONE) 49cfa460adSWilliam Juul writeb(cmd, this->IO_ADDR_W); 501a33ce65STsiChungLiew } 511a33ce65STsiChungLiew 521a33ce65STsiChungLiew int board_nand_init(struct nand_chip *nand) 531a33ce65STsiChungLiew { 54aa0d99fcSAlison Wang gpio_t *gpio = (gpio_t *) MMAP_GPIO; 551a33ce65STsiChungLiew 56e4f69d1bSTsiChung Liew /* 57e4f69d1bSTsiChung Liew * set up pin configuration - enabled 2nd output buffer's signals 58e4f69d1bSTsiChung Liew * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc) 59e4f69d1bSTsiChung Liew * to use nCE signal 60e4f69d1bSTsiChung Liew */ 61aa0d99fcSAlison Wang clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3); 62aa0d99fcSAlison Wang setbits_8(&gpio->pddr_timer, 0x08); 63aa0d99fcSAlison Wang setbits_8(&gpio->ppd_timer, 0x08); 64aa0d99fcSAlison Wang out_8(&gpio->pclrr_timer, 0); 65aa0d99fcSAlison Wang out_8(&gpio->podr_timer, 0); 661a33ce65STsiChungLiew 679017d932STsiChung Liew nand->chip_delay = 60; 68cfa460adSWilliam Juul nand->ecc.mode = NAND_ECC_SOFT; 69cfa460adSWilliam Juul nand->cmd_ctrl = nand_hwcontrol; 701a33ce65STsiChungLiew 711a33ce65STsiChungLiew return 0; 721a33ce65STsiChungLiew } 731a33ce65STsiChungLiew #endif 74