1*1a33ce65STsiChungLiew /* 2*1a33ce65STsiChungLiew * (C) Copyright 2000-2003 3*1a33ce65STsiChungLiew * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4*1a33ce65STsiChungLiew * 5*1a33ce65STsiChungLiew * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 6*1a33ce65STsiChungLiew * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7*1a33ce65STsiChungLiew * 8*1a33ce65STsiChungLiew * See file CREDITS for list of people who contributed to this 9*1a33ce65STsiChungLiew * project. 10*1a33ce65STsiChungLiew * 11*1a33ce65STsiChungLiew * This program is free software; you can redistribute it and/or 12*1a33ce65STsiChungLiew * modify it under the terms of the GNU General Public License as 13*1a33ce65STsiChungLiew * published by the Free Software Foundation; either version 2 of 14*1a33ce65STsiChungLiew * the License, or (at your option) any later version. 15*1a33ce65STsiChungLiew * 16*1a33ce65STsiChungLiew * This program is distributed in the hope that it will be useful, 17*1a33ce65STsiChungLiew * but WITHOUT ANY WARRANTY; without even the implied warranty of 18*1a33ce65STsiChungLiew * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19*1a33ce65STsiChungLiew * GNU General Public License for more details. 20*1a33ce65STsiChungLiew * 21*1a33ce65STsiChungLiew * You should have received a copy of the GNU General Public License 22*1a33ce65STsiChungLiew * along with this program; if not, write to the Free Software 23*1a33ce65STsiChungLiew * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24*1a33ce65STsiChungLiew * MA 02111-1307 USA 25*1a33ce65STsiChungLiew */ 26*1a33ce65STsiChungLiew 27*1a33ce65STsiChungLiew #include <config.h> 28*1a33ce65STsiChungLiew #include <common.h> 29*1a33ce65STsiChungLiew #include <asm/io.h> 30*1a33ce65STsiChungLiew #include <asm/immap.h> 31*1a33ce65STsiChungLiew 32*1a33ce65STsiChungLiew DECLARE_GLOBAL_DATA_PTR; 33*1a33ce65STsiChungLiew 34*1a33ce65STsiChungLiew #if (CONFIG_COMMANDS & CFG_CMD_NAND) 35*1a33ce65STsiChungLiew #include <nand.h> 36*1a33ce65STsiChungLiew #include <linux/mtd/mtd.h> 37*1a33ce65STsiChungLiew 38*1a33ce65STsiChungLiew #define SET_CLE 0x10 39*1a33ce65STsiChungLiew #define CLR_CLE ~SET_CLE 40*1a33ce65STsiChungLiew #define SET_ALE 0x08 41*1a33ce65STsiChungLiew #define CLR_ALE ~SET_ALE 42*1a33ce65STsiChungLiew 43*1a33ce65STsiChungLiew static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd) 44*1a33ce65STsiChungLiew { 45*1a33ce65STsiChungLiew struct nand_chip *this = mtdinfo->priv; 46*1a33ce65STsiChungLiew volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; 47*1a33ce65STsiChungLiew u32 nand_baseaddr = (u32) this->IO_ADDR_W; 48*1a33ce65STsiChungLiew 49*1a33ce65STsiChungLiew switch (cmd) { 50*1a33ce65STsiChungLiew case NAND_CTL_SETNCE: 51*1a33ce65STsiChungLiew case NAND_CTL_CLRNCE: 52*1a33ce65STsiChungLiew break; 53*1a33ce65STsiChungLiew case NAND_CTL_SETCLE: 54*1a33ce65STsiChungLiew nand_baseaddr |= SET_CLE; 55*1a33ce65STsiChungLiew break; 56*1a33ce65STsiChungLiew case NAND_CTL_CLRCLE: 57*1a33ce65STsiChungLiew nand_baseaddr &= CLR_CLE; 58*1a33ce65STsiChungLiew break; 59*1a33ce65STsiChungLiew case NAND_CTL_SETALE: 60*1a33ce65STsiChungLiew nand_baseaddr |= SET_ALE; 61*1a33ce65STsiChungLiew break; 62*1a33ce65STsiChungLiew case NAND_CTL_CLRALE: 63*1a33ce65STsiChungLiew nand_baseaddr |= CLR_ALE; 64*1a33ce65STsiChungLiew break; 65*1a33ce65STsiChungLiew case NAND_CTL_SETWP: 66*1a33ce65STsiChungLiew fbcs->csmr2 |= CSMR_WP; 67*1a33ce65STsiChungLiew break; 68*1a33ce65STsiChungLiew case NAND_CTL_CLRWP: 69*1a33ce65STsiChungLiew fbcs->csmr2 &= ~CSMR_WP; 70*1a33ce65STsiChungLiew break; 71*1a33ce65STsiChungLiew } 72*1a33ce65STsiChungLiew this->IO_ADDR_W = (void __iomem *)(nand_baseaddr); 73*1a33ce65STsiChungLiew } 74*1a33ce65STsiChungLiew 75*1a33ce65STsiChungLiew static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte) 76*1a33ce65STsiChungLiew { 77*1a33ce65STsiChungLiew struct nand_chip *this = mtdinfo->priv; 78*1a33ce65STsiChungLiew *((volatile u8 *)(this->IO_ADDR_W)) = byte; 79*1a33ce65STsiChungLiew } 80*1a33ce65STsiChungLiew 81*1a33ce65STsiChungLiew static u8 nand_read_byte(struct mtd_info *mtdinfo) 82*1a33ce65STsiChungLiew { 83*1a33ce65STsiChungLiew struct nand_chip *this = mtdinfo->priv; 84*1a33ce65STsiChungLiew return (u8) (*((volatile u8 *)this->IO_ADDR_R)); 85*1a33ce65STsiChungLiew } 86*1a33ce65STsiChungLiew 87*1a33ce65STsiChungLiew static int nand_dev_ready(struct mtd_info *mtdinfo) 88*1a33ce65STsiChungLiew { 89*1a33ce65STsiChungLiew return 1; 90*1a33ce65STsiChungLiew } 91*1a33ce65STsiChungLiew 92*1a33ce65STsiChungLiew int board_nand_init(struct nand_chip *nand) 93*1a33ce65STsiChungLiew { 94*1a33ce65STsiChungLiew volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; 95*1a33ce65STsiChungLiew 96*1a33ce65STsiChungLiew *((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004; 97*1a33ce65STsiChungLiew 98*1a33ce65STsiChungLiew /* set up pin configuration */ 99*1a33ce65STsiChungLiew gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3; 100*1a33ce65STsiChungLiew gpio->pddr_timer |= 0x08; 101*1a33ce65STsiChungLiew gpio->ppd_timer |= 0x08; 102*1a33ce65STsiChungLiew gpio->pclrr_timer = 0; 103*1a33ce65STsiChungLiew gpio->podr_timer = 0; 104*1a33ce65STsiChungLiew 105*1a33ce65STsiChungLiew nand->chip_delay = 50; 106*1a33ce65STsiChungLiew nand->eccmode = NAND_ECC_SOFT; 107*1a33ce65STsiChungLiew nand->hwcontrol = nand_hwcontrol; 108*1a33ce65STsiChungLiew nand->read_byte = nand_read_byte; 109*1a33ce65STsiChungLiew nand->write_byte = nand_write_byte; 110*1a33ce65STsiChungLiew nand->dev_ready = nand_dev_ready; 111*1a33ce65STsiChungLiew 112*1a33ce65STsiChungLiew return 0; 113*1a33ce65STsiChungLiew } 114*1a33ce65STsiChungLiew #endif 115*1a33ce65STsiChungLiew 116