1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2000-2003
4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5  */
6 
7 #include <common.h>
8 #include <asm/immap.h>
9 
10 DECLARE_GLOBAL_DATA_PTR;
11 
12 int checkboard (void)
13 {
14 	puts ("Board: Freescale M5282EVB Evaluation Board\n");
15 	return 0;
16 }
17 
18 int dram_init(void)
19 {
20 	u32 dramsize, i, dramclk;
21 
22 	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
23 	for (i = 0x13; i < 0x20; i++) {
24 		if (dramsize == (1 << i))
25 			break;
26 	}
27 	i--;
28 
29 	if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE))
30 	{
31 		dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
32 
33 		/* Initialize DRAM Control Register: DCR */
34 		MCFSDRAMC_DCR = (0
35 			| MCFSDRAMC_DCR_RTIM_6
36 			| MCFSDRAMC_DCR_RC((15 * dramclk)>>4));
37 		asm("nop");
38 
39 		/* Initialize DACR0 */
40 		MCFSDRAMC_DACR0 = (0
41 			| MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE)
42 			| MCFSDRAMC_DACR_CASL(1)
43 			| MCFSDRAMC_DACR_CBM(3)
44 			| MCFSDRAMC_DACR_PS_32);
45 		asm("nop");
46 
47 		/* Initialize DMR0 */
48 		MCFSDRAMC_DMR0 = (0
49 			| ((dramsize - 1) & 0xFFFC0000)
50 			| MCFSDRAMC_DMR_V);
51 		asm("nop");
52 
53 		/* Set IP (bit 3) in DACR */
54 		MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
55 		asm("nop");
56 
57 		/* Wait 30ns to allow banks to precharge */
58 		for (i = 0; i < 5; i++) {
59 			asm ("nop");
60 		}
61 
62 		/* Write to this block to initiate precharge */
63 		*(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
64 		asm("nop");
65 
66 		/* Set RE (bit 15) in DACR */
67 		MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
68 		asm("nop");
69 
70 		/* Wait for at least 8 auto refresh cycles to occur */
71 		for (i = 0; i < 2000; i++) {
72 			asm(" nop");
73 		}
74 
75 		/* Finish the configuration by issuing the IMRS. */
76 		MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
77 		asm("nop");
78 
79 		/* Write to the SDRAM Mode Register */
80 		*(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
81 	}
82 	gd->ram_size = dramsize;
83 
84 	return 0;
85 }
86