1 /* 2 * (C) Copyright 2000-2003 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <asm/immap.h> 28 29 #define PERIOD 13 /* system bus period in ns */ 30 #define SDRAM_TREFI 7800 /* in ns */ 31 32 int checkboard(void) 33 { 34 puts("Board: "); 35 puts("Freescale MCF5275 EVB\n"); 36 return 0; 37 }; 38 39 phys_size_t initdram(int board_type) 40 { 41 volatile sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM); 42 volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO); 43 44 gpio_reg->par_sdram = 0x3FF; /* Enable SDRAM */ 45 46 /* Set up chip select */ 47 sdp->sdbar0 = CONFIG_SYS_SDRAM_BASE; 48 sdp->sdbmr0 = MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V; 49 50 /* Set up timing */ 51 sdp->sdcfg1 = 0x83711630; 52 sdp->sdcfg2 = 0x46770000; 53 54 /* Enable clock */ 55 sdp->sdcr = MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE; 56 57 /* Set precharge */ 58 sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL; 59 60 /* Dummy write to start SDRAM */ 61 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; 62 63 /* Send LEMR */ 64 sdp->sdmr = MCF_SDRAMC_SDMR_BNKAD_LEMR 65 | MCF_SDRAMC_SDMR_AD(0x0) 66 | MCF_SDRAMC_SDMR_CMD; 67 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; 68 69 /* Send LMR */ 70 sdp->sdmr = 0x058d0000; 71 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; 72 73 /* Stop sending commands */ 74 sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD); 75 76 /* Set precharge */ 77 sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL; 78 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; 79 80 /* Stop manual precharge, send 2 IREF */ 81 sdp->sdcr &= ~(MCF_SDRAMC_SDCR_IPALL); 82 sdp->sdcr |= MCF_SDRAMC_SDCR_IREF; 83 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; 84 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; 85 86 /* Write mode register, clear reset DLL */ 87 sdp->sdmr = 0x018d0000; 88 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; 89 90 /* Stop sending commands */ 91 sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD); 92 sdp->sdcr &= ~(MCF_SDRAMC_SDCR_MODE_EN); 93 94 /* Turn on auto refresh, lock SDMR */ 95 sdp->sdcr = 96 MCF_SDRAMC_SDCR_CKE 97 | MCF_SDRAMC_SDCR_REF 98 | MCF_SDRAMC_SDCR_MUX(1) 99 /* 1 added to round up */ 100 | MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1) 101 | MCF_SDRAMC_SDCR_DQS_OE(0x3); 102 103 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 104 }; 105 106 int testdram(void) 107 { 108 /* TODO: XXX XXX XXX */ 109 printf("DRAM test not implemented!\n"); 110 111 return (0); 112 } 113