1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2545c8e0aSMatthew Fettke /*
3545c8e0aSMatthew Fettke * (C) Copyright 2000-2003
4545c8e0aSMatthew Fettke * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5545c8e0aSMatthew Fettke *
6545c8e0aSMatthew Fettke * Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com)
7545c8e0aSMatthew Fettke *
832dbaafaSAlison Wang * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
9545c8e0aSMatthew Fettke */
10545c8e0aSMatthew Fettke
11545c8e0aSMatthew Fettke #include <common.h>
12545c8e0aSMatthew Fettke #include <asm/immap.h>
1332dbaafaSAlison Wang #include <asm/io.h>
14545c8e0aSMatthew Fettke
15088454cdSSimon Glass DECLARE_GLOBAL_DATA_PTR;
16088454cdSSimon Glass
17545c8e0aSMatthew Fettke #define PERIOD 13 /* system bus period in ns */
18545c8e0aSMatthew Fettke #define SDRAM_TREFI 7800 /* in ns */
19545c8e0aSMatthew Fettke
checkboard(void)20545c8e0aSMatthew Fettke int checkboard(void)
21545c8e0aSMatthew Fettke {
22545c8e0aSMatthew Fettke puts("Board: ");
23545c8e0aSMatthew Fettke puts("Freescale MCF5275 EVB\n");
24545c8e0aSMatthew Fettke return 0;
25545c8e0aSMatthew Fettke };
26545c8e0aSMatthew Fettke
dram_init(void)27f1683aa7SSimon Glass int dram_init(void)
28545c8e0aSMatthew Fettke {
2932dbaafaSAlison Wang sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
3032dbaafaSAlison Wang gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
31545c8e0aSMatthew Fettke
3232dbaafaSAlison Wang /* Enable SDRAM */
3332dbaafaSAlison Wang out_be16(&gpio_reg->par_sdram, 0x3FF);
34545c8e0aSMatthew Fettke
35545c8e0aSMatthew Fettke /* Set up chip select */
3632dbaafaSAlison Wang out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE);
3732dbaafaSAlison Wang out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V);
38545c8e0aSMatthew Fettke
39545c8e0aSMatthew Fettke /* Set up timing */
4032dbaafaSAlison Wang out_be32(&sdp->sdcfg1, 0x83711630);
4132dbaafaSAlison Wang out_be32(&sdp->sdcfg2, 0x46770000);
42545c8e0aSMatthew Fettke
43545c8e0aSMatthew Fettke /* Enable clock */
4432dbaafaSAlison Wang out_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE);
45545c8e0aSMatthew Fettke
46545c8e0aSMatthew Fettke /* Set precharge */
4732dbaafaSAlison Wang setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
48545c8e0aSMatthew Fettke
49545c8e0aSMatthew Fettke /* Dummy write to start SDRAM */
506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
51545c8e0aSMatthew Fettke
52545c8e0aSMatthew Fettke /* Send LEMR */
5332dbaafaSAlison Wang setbits_be32(&sdp->sdmr,
5432dbaafaSAlison Wang MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) |
5532dbaafaSAlison Wang MCF_SDRAMC_SDMR_CMD);
566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
57545c8e0aSMatthew Fettke
58545c8e0aSMatthew Fettke /* Send LMR */
5932dbaafaSAlison Wang out_be32(&sdp->sdmr, 0x058d0000);
606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
61545c8e0aSMatthew Fettke
62545c8e0aSMatthew Fettke /* Stop sending commands */
6332dbaafaSAlison Wang clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
64545c8e0aSMatthew Fettke
65545c8e0aSMatthew Fettke /* Set precharge */
6632dbaafaSAlison Wang setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
68545c8e0aSMatthew Fettke
69545c8e0aSMatthew Fettke /* Stop manual precharge, send 2 IREF */
7032dbaafaSAlison Wang clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
7132dbaafaSAlison Wang setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF);
726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
74545c8e0aSMatthew Fettke
7532dbaafaSAlison Wang
7632dbaafaSAlison Wang out_be32(&sdp->sdmr, 0x018d0000);
776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
78545c8e0aSMatthew Fettke
79545c8e0aSMatthew Fettke /* Stop sending commands */
8032dbaafaSAlison Wang clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
8132dbaafaSAlison Wang clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN);
82545c8e0aSMatthew Fettke
83545c8e0aSMatthew Fettke /* Turn on auto refresh, lock SDMR */
8432dbaafaSAlison Wang out_be32(&sdp->sdcr,
85545c8e0aSMatthew Fettke MCF_SDRAMC_SDCR_CKE
86545c8e0aSMatthew Fettke | MCF_SDRAMC_SDCR_REF
87545c8e0aSMatthew Fettke | MCF_SDRAMC_SDCR_MUX(1)
88545c8e0aSMatthew Fettke /* 1 added to round up */
89545c8e0aSMatthew Fettke | MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
9032dbaafaSAlison Wang | MCF_SDRAMC_SDCR_DQS_OE(0x3));
91545c8e0aSMatthew Fettke
92088454cdSSimon Glass gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
93088454cdSSimon Glass
94088454cdSSimon Glass return 0;
95545c8e0aSMatthew Fettke };
96545c8e0aSMatthew Fettke
testdram(void)97545c8e0aSMatthew Fettke int testdram(void)
98545c8e0aSMatthew Fettke {
99545c8e0aSMatthew Fettke /* TODO: XXX XXX XXX */
100545c8e0aSMatthew Fettke printf("DRAM test not implemented!\n");
101545c8e0aSMatthew Fettke
102545c8e0aSMatthew Fettke return (0);
103545c8e0aSMatthew Fettke }
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