1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2000-2003
4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5  *
6  * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
7  * Hayden Fraser (Hayden.Fraser@freescale.com)
8  */
9 
10 #include <common.h>
11 #include <asm/immap.h>
12 #include <netdev.h>
13 #include <asm/io.h>
14 
15 DECLARE_GLOBAL_DATA_PTR;
16 
17 int checkboard(void)
18 {
19 	puts("Board: ");
20 	puts("Freescale MCF5253 DEMO\n");
21 	return 0;
22 };
23 
24 int dram_init(void)
25 {
26 	u32 dramsize = 0;
27 
28 	/*
29 	 * Check to see if the SDRAM has already been initialized
30 	 * by a run control tool
31 	 */
32 	if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
33 		u32 RC, temp;
34 
35 		RC = (CONFIG_SYS_CLK / 1000000) >> 1;
36 		RC = (RC * 15) >> 4;
37 
38 		/* Initialize DRAM Control Register: DCR */
39 		mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
40 		__asm__("nop");
41 
42 		mbar_writeLong(MCFSIM_DACR0, 0x00003224);
43 		__asm__("nop");
44 
45 		/* Initialize DMR0 */
46 		dramsize = (CONFIG_SYS_SDRAM_SIZE << 20);
47 		temp = (dramsize - 1) & 0xFFFC0000;
48 		mbar_writeLong(MCFSIM_DMR0, temp | 1);
49 		__asm__("nop");
50 
51 		mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
52 		mb();
53 		__asm__("nop");
54 
55 		/* Write to this block to initiate precharge */
56 		*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
57 		mb();
58 		__asm__("nop");
59 
60 		/* Set RE bit in DACR */
61 		mbar_writeLong(MCFSIM_DACR0,
62 			       mbar_readLong(MCFSIM_DACR0) | 0x8000);
63 		__asm__("nop");
64 
65 		/* Wait for at least 8 auto refresh cycles to occur */
66 		udelay(500);
67 
68 		/* Finish the configuration by issuing the MRS */
69 		mbar_writeLong(MCFSIM_DACR0,
70 			       mbar_readLong(MCFSIM_DACR0) | 0x0040);
71 		__asm__("nop");
72 
73 		*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
74 		mb();
75 	}
76 
77 	gd->ram_size = dramsize;
78 
79 	return 0;
80 }
81 
82 int testdram(void)
83 {
84 	/* TODO: XXX XXX XXX */
85 	printf("DRAM test not implemented!\n");
86 
87 	return (0);
88 }
89 
90 #ifdef CONFIG_IDE
91 #include <ata.h>
92 int ide_preinit(void)
93 {
94 	return (0);
95 }
96 
97 void ide_set_reset(int idereset)
98 {
99 	atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
100 	long period;
101 	/*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
102 	int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35},	/* PIO 0 */
103 	{50, 125, 45, 20, 35, 5, 15, 0, 35},	/* PIO 1 */
104 	{30, 100, 30, 15, 20, 5, 10, 0, 35},	/* PIO 2 */
105 	{30, 80, 30, 10, 20, 5, 10, 0, 35},	/* PIO 3 */
106 	{25, 70, 20, 10, 20, 5, 10, 0, 35}	/* PIO 4 */
107 	};
108 
109 	if (idereset) {
110 		/* control reset */
111 		out_8(&ata->cr, 0);
112 		udelay(100);
113 	} else {
114 		mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
115 
116 #define CALC_TIMING(t) (t + period - 1) / period
117 		period = 1000000000 / (CONFIG_SYS_CLK / 2);	/* period in ns */
118 
119 		/*ata->ton = CALC_TIMING (180); */
120 		out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
121 		out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
122 		out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
123 		out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
124 		out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
125 		out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
126 		out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
127 
128 		/* IORDY enable */
129 		out_8(&ata->cr, 0x40);
130 		udelay(2000);
131 		/* IORDY enable */
132 		setbits_8(&ata->cr, 0x01);
133 	}
134 }
135 #endif				/* CONFIG_IDE */
136 
137 
138 #ifdef CONFIG_DRIVER_DM9000
139 int board_eth_init(bd_t *bis)
140 {
141 	return dm9000_initialize(bis);
142 }
143 #endif
144