1 /* 2 * (C) Copyright 2000-2003 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 6 * Hayden Fraser (Hayden.Fraser@freescale.com) 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 #include <common.h> 28 #include <asm/immap.h> 29 #include <netdev.h> 30 #include <asm/io.h> 31 32 int checkboard(void) 33 { 34 puts("Board: "); 35 puts("Freescale MCF5253 DEMO\n"); 36 return 0; 37 }; 38 39 phys_size_t initdram(int board_type) 40 { 41 u32 dramsize = 0; 42 43 /* 44 * Check to see if the SDRAM has already been initialized 45 * by a run control tool 46 */ 47 if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) { 48 u32 RC, temp; 49 50 RC = (CONFIG_SYS_CLK / 1000000) >> 1; 51 RC = (RC * 15) >> 4; 52 53 /* Initialize DRAM Control Register: DCR */ 54 mbar_writeShort(MCFSIM_DCR, (0x8400 | RC)); 55 __asm__("nop"); 56 57 mbar_writeLong(MCFSIM_DACR0, 0x00003224); 58 __asm__("nop"); 59 60 /* Initialize DMR0 */ 61 dramsize = (CONFIG_SYS_SDRAM_SIZE << 20); 62 temp = (dramsize - 1) & 0xFFFC0000; 63 mbar_writeLong(MCFSIM_DMR0, temp | 1); 64 __asm__("nop"); 65 66 mbar_writeLong(MCFSIM_DACR0, 0x0000322c); 67 mb(); 68 __asm__("nop"); 69 70 /* Write to this block to initiate precharge */ 71 *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5; 72 mb(); 73 __asm__("nop"); 74 75 /* Set RE bit in DACR */ 76 mbar_writeLong(MCFSIM_DACR0, 77 mbar_readLong(MCFSIM_DACR0) | 0x8000); 78 __asm__("nop"); 79 80 /* Wait for at least 8 auto refresh cycles to occur */ 81 udelay(500); 82 83 /* Finish the configuration by issuing the MRS */ 84 mbar_writeLong(MCFSIM_DACR0, 85 mbar_readLong(MCFSIM_DACR0) | 0x0040); 86 __asm__("nop"); 87 88 *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5; 89 mb(); 90 } 91 92 return dramsize; 93 } 94 95 int testdram(void) 96 { 97 /* TODO: XXX XXX XXX */ 98 printf("DRAM test not implemented!\n"); 99 100 return (0); 101 } 102 103 #ifdef CONFIG_CMD_IDE 104 #include <ata.h> 105 int ide_preinit(void) 106 { 107 return (0); 108 } 109 110 void ide_set_reset(int idereset) 111 { 112 volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR; 113 long period; 114 /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ 115 int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ 116 {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */ 117 {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */ 118 {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */ 119 {25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */ 120 }; 121 122 if (idereset) { 123 ata->cr = 0; /* control reset */ 124 udelay(100); 125 } else { 126 mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND); 127 128 #define CALC_TIMING(t) (t + period - 1) / period 129 period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */ 130 131 /*ata->ton = CALC_TIMING (180); */ 132 ata->t1 = CALC_TIMING(piotms[2][0]); 133 ata->t2w = CALC_TIMING(piotms[2][1]); 134 ata->t2r = CALC_TIMING(piotms[2][1]); 135 ata->ta = CALC_TIMING(piotms[2][8]); 136 ata->trd = CALC_TIMING(piotms[2][7]); 137 ata->t4 = CALC_TIMING(piotms[2][3]); 138 ata->t9 = CALC_TIMING(piotms[2][6]); 139 140 ata->cr = 0x40; /* IORDY enable */ 141 udelay(2000); 142 ata->cr |= 0x01; /* IORDY enable */ 143 } 144 } 145 #endif /* CONFIG_CMD_IDE */ 146 147 148 #ifdef CONFIG_DRIVER_DM9000 149 int board_eth_init(bd_t *bis) 150 { 151 return dm9000_initialize(bis); 152 } 153 #endif 154