1 /* 2 * (C) Copyright 2000-2003 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 6 * Hayden Fraser (Hayden.Fraser@freescale.com) 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 #include <common.h> 28 #include <asm/immap.h> 29 #include <netdev.h> 30 31 int checkboard(void) 32 { 33 puts("Board: "); 34 puts("Freescale MCF5253 DEMO\n"); 35 return 0; 36 }; 37 38 phys_size_t initdram(int board_type) 39 { 40 u32 dramsize = 0; 41 42 /* 43 * Check to see if the SDRAM has already been initialized 44 * by a run control tool 45 */ 46 if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) { 47 u32 RC, temp; 48 49 RC = (CONFIG_SYS_CLK / 1000000) >> 1; 50 RC = (RC * 15) >> 4; 51 52 /* Initialize DRAM Control Register: DCR */ 53 mbar_writeShort(MCFSIM_DCR, (0x8400 | RC)); 54 __asm__("nop"); 55 56 mbar_writeLong(MCFSIM_DACR0, 0x00003224); 57 __asm__("nop"); 58 59 /* Initialize DMR0 */ 60 dramsize = (CONFIG_SYS_SDRAM_SIZE << 20); 61 temp = (dramsize - 1) & 0xFFFC0000; 62 mbar_writeLong(MCFSIM_DMR0, temp | 1); 63 __asm__("nop"); 64 65 mbar_writeLong(MCFSIM_DACR0, 0x0000322c); 66 __asm__("nop"); 67 68 /* Write to this block to initiate precharge */ 69 *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5; 70 __asm__("nop"); 71 72 /* Set RE bit in DACR */ 73 mbar_writeLong(MCFSIM_DACR0, 74 mbar_readLong(MCFSIM_DACR0) | 0x8000); 75 __asm__("nop"); 76 77 /* Wait for at least 8 auto refresh cycles to occur */ 78 udelay(500); 79 80 /* Finish the configuration by issuing the MRS */ 81 mbar_writeLong(MCFSIM_DACR0, 82 mbar_readLong(MCFSIM_DACR0) | 0x0040); 83 __asm__("nop"); 84 85 *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5; 86 } 87 88 return dramsize; 89 } 90 91 int testdram(void) 92 { 93 /* TODO: XXX XXX XXX */ 94 printf("DRAM test not implemented!\n"); 95 96 return (0); 97 } 98 99 #ifdef CONFIG_CMD_IDE 100 #include <ata.h> 101 int ide_preinit(void) 102 { 103 return (0); 104 } 105 106 void ide_set_reset(int idereset) 107 { 108 volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR; 109 long period; 110 /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ 111 int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ 112 {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */ 113 {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */ 114 {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */ 115 {25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */ 116 }; 117 118 if (idereset) { 119 ata->cr = 0; /* control reset */ 120 udelay(100); 121 } else { 122 mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND); 123 124 #define CALC_TIMING(t) (t + period - 1) / period 125 period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */ 126 127 /*ata->ton = CALC_TIMING (180); */ 128 ata->t1 = CALC_TIMING(piotms[2][0]); 129 ata->t2w = CALC_TIMING(piotms[2][1]); 130 ata->t2r = CALC_TIMING(piotms[2][1]); 131 ata->ta = CALC_TIMING(piotms[2][8]); 132 ata->trd = CALC_TIMING(piotms[2][7]); 133 ata->t4 = CALC_TIMING(piotms[2][3]); 134 ata->t9 = CALC_TIMING(piotms[2][6]); 135 136 ata->cr = 0x40; /* IORDY enable */ 137 udelay(2000); 138 ata->cr |= 0x01; /* IORDY enable */ 139 } 140 } 141 #endif /* CONFIG_CMD_IDE */ 142 143 144 #ifdef CONFIG_DRIVER_DM9000 145 int board_eth_init(bd_t *bis) 146 { 147 return dm9000_initialize(bis); 148 } 149 #endif 150