1 /*
2  * (C) Copyright 2000-2003
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  *
5  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6  * Hayden Fraser (Hayden.Fraser@freescale.com)
7  *
8  * See file CREDITS for list of people who contributed to this
9  * project.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License as
13  * published by the Free Software Foundation; either version 2 of
14  * the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24  * MA 02111-1307 USA
25  */
26 
27 #include <common.h>
28 #include <asm/immap.h>
29 
30 int checkboard(void)
31 {
32 	puts("Board: ");
33 	puts("Freescale MCF5253 DEMO\n");
34 	return 0;
35 };
36 
37 phys_size_t initdram(int board_type)
38 {
39 	u32 dramsize = 0;
40 
41 	/*
42 	 * Check to see if the SDRAM has already been initialized
43 	 * by a run control tool
44 	 */
45 	if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
46 		u32 RC, temp;
47 
48 		RC = (CFG_CLK / 1000000) >> 1;
49 		RC = (RC * 15) >> 4;
50 
51 		/* Initialize DRAM Control Register: DCR */
52 		mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
53 		__asm__("nop");
54 
55 		mbar_writeLong(MCFSIM_DACR0, 0x00003224);
56 		__asm__("nop");
57 
58 		/* Initialize DMR0 */
59 		dramsize = (CFG_SDRAM_SIZE << 20);
60 		temp = (dramsize - 1) & 0xFFFC0000;
61 		mbar_writeLong(MCFSIM_DMR0, temp | 1);
62 		__asm__("nop");
63 
64 		mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
65 		__asm__("nop");
66 
67 		/* Write to this block to initiate precharge */
68 		*(u32 *) (CFG_SDRAM_BASE) = 0xa5a5a5a5;
69 		__asm__("nop");
70 
71 		/* Set RE bit in DACR */
72 		mbar_writeLong(MCFSIM_DACR0,
73 			       mbar_readLong(MCFSIM_DACR0) | 0x8000);
74 		__asm__("nop");
75 
76 		/* Wait for at least 8 auto refresh cycles to occur */
77 		udelay(500);
78 
79 		/* Finish the configuration by issuing the MRS */
80 		mbar_writeLong(MCFSIM_DACR0,
81 			       mbar_readLong(MCFSIM_DACR0) | 0x0040);
82 		__asm__("nop");
83 
84 		*(u32 *) (CFG_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
85 	}
86 
87 	return dramsize;
88 }
89 
90 int testdram(void)
91 {
92 	/* TODO: XXX XXX XXX */
93 	printf("DRAM test not implemented!\n");
94 
95 	return (0);
96 }
97 
98 #ifdef CONFIG_CMD_IDE
99 #include <ata.h>
100 int ide_preinit(void)
101 {
102 	return (0);
103 }
104 
105 void ide_set_reset(int idereset)
106 {
107 	volatile atac_t *ata = (atac_t *) CFG_ATA_BASE_ADDR;
108 	long period;
109 	/*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
110 	int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35},	/* PIO 0 */
111 	{50, 125, 45, 20, 35, 5, 15, 0, 35},	/* PIO 1 */
112 	{30, 100, 30, 15, 20, 5, 10, 0, 35},	/* PIO 2 */
113 	{30, 80, 30, 10, 20, 5, 10, 0, 35},	/* PIO 3 */
114 	{25, 70, 20, 10, 20, 5, 10, 0, 35}	/* PIO 4 */
115 	};
116 
117 	if (idereset) {
118 		ata->cr = 0;	/* control reset */
119 		udelay(100);
120 	} else {
121 		mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
122 
123 #define CALC_TIMING(t) (t + period - 1) / period
124 		period = 1000000000 / (CFG_CLK / 2);	/* period in ns */
125 
126 		/*ata->ton = CALC_TIMING (180); */
127 		ata->t1 = CALC_TIMING(piotms[2][0]);
128 		ata->t2w = CALC_TIMING(piotms[2][1]);
129 		ata->t2r = CALC_TIMING(piotms[2][1]);
130 		ata->ta = CALC_TIMING(piotms[2][8]);
131 		ata->trd = CALC_TIMING(piotms[2][7]);
132 		ata->t4 = CALC_TIMING(piotms[2][3]);
133 		ata->t9 = CALC_TIMING(piotms[2][6]);
134 
135 		ata->cr = 0x40;	/* IORDY enable */
136 		udelay(2000);
137 		ata->cr |= 0x01;	/* IORDY enable */
138 	}
139 }
140 #endif				/* CONFIG_CMD_IDE */
141