1 /*
2  * (C) Copyright 2000-2003
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  *
5  * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7  *
8  * See file CREDITS for list of people who contributed to this
9  * project.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License as
13  * published by the Free Software Foundation; either version 2 of
14  * the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24  * MA 02111-1307 USA
25  */
26 
27 #include <config.h>
28 #include <common.h>
29 #include <asm/immap.h>
30 #include <asm/io.h>
31 
32 DECLARE_GLOBAL_DATA_PTR;
33 
34 int checkboard(void)
35 {
36 	puts("Board: ");
37 	puts("Freescale M5235 EVB\n");
38 	return 0;
39 };
40 
41 phys_size_t initdram(int board_type)
42 {
43 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
44 	gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
45 	u32 dramsize, i, dramclk;
46 
47 	/*
48 	 * When booting from external Flash, the port-size is less than
49 	 * the port-size of SDRAM.  In this case it is necessary to enable
50 	 * Data[15:0] on Port Address/Data.
51 	 */
52 	out_8(&gpio->par_ad,
53 		GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 |
54 		GPIO_PAR_AD_DATAL);
55 
56 	/* Initialize PAR to enable SDRAM signals */
57 	out_8(&gpio->par_sdram,
58 		GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS |
59 		GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE |
60 		GPIO_PAR_SDRAM_SDCS(3));
61 
62 	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
63 	for (i = 0x13; i < 0x20; i++) {
64 		if (dramsize == (1 << i))
65 			break;
66 	}
67 	i--;
68 
69 	if (!(in_be32(&sdram->dacr0) & SDRAMC_DARCn_RE)) {
70 		dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
71 
72 		/* Initialize DRAM Control Register: DCR */
73 		out_be16(&sdram->dcr, SDRAMC_DCR_RTIM_9CLKS |
74 			SDRAMC_DCR_RTIM_6CLKS |
75 			SDRAMC_DCR_RC((15 * dramclk) >> 4));
76 
77 		/* Initialize DACR0 */
78 		out_be32(&sdram->dacr0,
79 			SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) |
80 			SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 |
81 			SDRAMC_DARCn_PS_32);
82 		asm("nop");
83 
84 		/* Initialize DMR0 */
85 		out_be32(&sdram->dmr0,
86 			((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V);
87 		asm("nop");
88 
89 		/* Set IP (bit 3) in DACR */
90 		setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IP);
91 
92 		/* Wait 30ns to allow banks to precharge */
93 		for (i = 0; i < 5; i++) {
94 			asm("nop");
95 		}
96 
97 		/* Write to this block to initiate precharge */
98 		*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
99 
100 		/*  Set RE (bit 15) in DACR */
101 		setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE);
102 
103 		/* Wait for at least 8 auto refresh cycles to occur */
104 		for (i = 0; i < 0x2000; i++) {
105 			asm("nop");
106 		}
107 
108 		/* Finish the configuration by issuing the MRS. */
109 		setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IMRS);
110 		asm("nop");
111 
112 		/* Write to the SDRAM Mode Register */
113 		*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
114 	}
115 
116 	return dramsize;
117 };
118 
119 int testdram(void)
120 {
121 	/* TODO: XXX XXX XXX */
122 	printf("DRAM test not implemented!\n");
123 
124 	return (0);
125 }
126