1 /* 2 * (C) Copyright 2000-2003 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 #include <config.h> 28 #include <common.h> 29 #include <asm/immap.h> 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 int checkboard(void) 34 { 35 puts("Board: "); 36 puts("Freescale M5235 EVB\n"); 37 return 0; 38 }; 39 40 phys_size_t initdram(int board_type) 41 { 42 volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); 43 volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); 44 u32 dramsize, i, dramclk; 45 46 /* 47 * When booting from external Flash, the port-size is less than 48 * the port-size of SDRAM. In this case it is necessary to enable 49 * Data[15:0] on Port Address/Data. 50 */ 51 gpio->par_ad = 52 GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 | 53 GPIO_PAR_AD_DATAL; 54 55 /* Initialize PAR to enable SDRAM signals */ 56 gpio->par_sdram = 57 GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | GPIO_PAR_SDRAM_SRAS | 58 GPIO_PAR_SDRAM_SCKE | GPIO_PAR_SDRAM_SDCS(3); 59 60 dramsize = CFG_SDRAM_SIZE * 0x100000; 61 for (i = 0x13; i < 0x20; i++) { 62 if (dramsize == (1 << i)) 63 break; 64 } 65 i--; 66 67 if (!(sdram->dacr0 & SDRAMC_DARCn_RE)) { 68 dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ); 69 70 /* Initialize DRAM Control Register: DCR */ 71 sdram->dcr = SDRAMC_DCR_RTIM_9CLKS | 72 SDRAMC_DCR_RTIM_6CLKS | SDRAMC_DCR_RC((15 * dramclk) >> 4); 73 74 /* Initialize DACR0 */ 75 sdram->dacr0 = 76 SDRAMC_DARCn_BA(CFG_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 | 77 SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32; 78 79 /* Initialize DMR0 */ 80 sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V; 81 82 /* Set IP (bit 3) in DACR */ 83 sdram->dacr0 |= SDRAMC_DARCn_IP; 84 85 /* Wait 30ns to allow banks to precharge */ 86 for (i = 0; i < 5; i++) { 87 asm("nop"); 88 } 89 90 /* Write to this block to initiate precharge */ 91 *(u32 *) (CFG_SDRAM_BASE) = 0xA5A59696; 92 93 /* Set RE (bit 15) in DACR */ 94 sdram->dacr0 |= SDRAMC_DARCn_RE; 95 96 /* Wait for at least 8 auto refresh cycles to occur */ 97 for (i = 0; i < 0x2000; i++) { 98 asm("nop"); 99 } 100 101 /* Finish the configuration by issuing the MRS. */ 102 sdram->dacr0 |= SDRAMC_DARCn_IMRS; 103 104 /* Write to the SDRAM Mode Register */ 105 *(u32 *) (CFG_SDRAM_BASE + 0x400) = 0xA5A59696; 106 } 107 108 return dramsize; 109 }; 110 111 int testdram(void) 112 { 113 /* TODO: XXX XXX XXX */ 114 printf("DRAM test not implemented!\n"); 115 116 return (0); 117 } 118