1*58c3e620SPriyanka Jain // SPDX-License-Identifier: GPL-2.0+ 2*58c3e620SPriyanka Jain /* 3*58c3e620SPriyanka Jain * Copyright 2018 NXP 4*58c3e620SPriyanka Jain * 5*58c3e620SPriyanka Jain */ 6*58c3e620SPriyanka Jain 7*58c3e620SPriyanka Jain #include <common.h> 8*58c3e620SPriyanka Jain #include <command.h> 9*58c3e620SPriyanka Jain #include <netdev.h> 10*58c3e620SPriyanka Jain #include <malloc.h> 11*58c3e620SPriyanka Jain #include <fsl_mdio.h> 12*58c3e620SPriyanka Jain #include <miiphy.h> 13*58c3e620SPriyanka Jain #include <phy.h> 14*58c3e620SPriyanka Jain #include <fm_eth.h> 15*58c3e620SPriyanka Jain #include <asm/io.h> 16*58c3e620SPriyanka Jain #include <exports.h> 17*58c3e620SPriyanka Jain #include <asm/arch/fsl_serdes.h> 18*58c3e620SPriyanka Jain #include <fsl-mc/fsl_mc.h> 19*58c3e620SPriyanka Jain #include <fsl-mc/ldpaa_wriop.h> 20*58c3e620SPriyanka Jain 21*58c3e620SPriyanka Jain DECLARE_GLOBAL_DATA_PTR; 22*58c3e620SPriyanka Jain 23*58c3e620SPriyanka Jain static bool get_inphi_phy_id(struct mii_dev *bus, int addr, int devad) 24*58c3e620SPriyanka Jain { 25*58c3e620SPriyanka Jain int phy_reg; 26*58c3e620SPriyanka Jain u32 phy_id; 27*58c3e620SPriyanka Jain 28*58c3e620SPriyanka Jain phy_reg = bus->read(bus, addr, devad, MII_PHYSID1); 29*58c3e620SPriyanka Jain phy_id = (phy_reg & 0xffff) << 16; 30*58c3e620SPriyanka Jain 31*58c3e620SPriyanka Jain phy_reg = bus->read(bus, addr, devad, MII_PHYSID2); 32*58c3e620SPriyanka Jain phy_id |= (phy_reg & 0xffff); 33*58c3e620SPriyanka Jain 34*58c3e620SPriyanka Jain if (phy_id == PHY_UID_IN112525_S03) 35*58c3e620SPriyanka Jain return true; 36*58c3e620SPriyanka Jain else 37*58c3e620SPriyanka Jain return false; 38*58c3e620SPriyanka Jain } 39*58c3e620SPriyanka Jain 40*58c3e620SPriyanka Jain int board_eth_init(bd_t *bis) 41*58c3e620SPriyanka Jain { 42*58c3e620SPriyanka Jain #if defined(CONFIG_FSL_MC_ENET) 43*58c3e620SPriyanka Jain struct memac_mdio_info mdio_info; 44*58c3e620SPriyanka Jain struct memac_mdio_controller *reg; 45*58c3e620SPriyanka Jain int i, interface; 46*58c3e620SPriyanka Jain struct mii_dev *dev; 47*58c3e620SPriyanka Jain struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 48*58c3e620SPriyanka Jain u32 srds_s1; 49*58c3e620SPriyanka Jain 50*58c3e620SPriyanka Jain srds_s1 = in_le32(&gur->rcwsr[28]) & 51*58c3e620SPriyanka Jain FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; 52*58c3e620SPriyanka Jain srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; 53*58c3e620SPriyanka Jain 54*58c3e620SPriyanka Jain reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; 55*58c3e620SPriyanka Jain mdio_info.regs = reg; 56*58c3e620SPriyanka Jain mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME; 57*58c3e620SPriyanka Jain 58*58c3e620SPriyanka Jain /* Register the EMI 1 */ 59*58c3e620SPriyanka Jain fm_memac_mdio_init(bis, &mdio_info); 60*58c3e620SPriyanka Jain 61*58c3e620SPriyanka Jain reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2; 62*58c3e620SPriyanka Jain mdio_info.regs = reg; 63*58c3e620SPriyanka Jain mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; 64*58c3e620SPriyanka Jain 65*58c3e620SPriyanka Jain /* Register the EMI 2 */ 66*58c3e620SPriyanka Jain fm_memac_mdio_init(bis, &mdio_info); 67*58c3e620SPriyanka Jain 68*58c3e620SPriyanka Jain dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); 69*58c3e620SPriyanka Jain switch (srds_s1) { 70*58c3e620SPriyanka Jain case 19: 71*58c3e620SPriyanka Jain wriop_set_phy_address(WRIOP1_DPMAC2, 0, 72*58c3e620SPriyanka Jain CORTINA_PHY_ADDR1); 73*58c3e620SPriyanka Jain wriop_set_phy_address(WRIOP1_DPMAC3, 0, 74*58c3e620SPriyanka Jain AQR107_PHY_ADDR1); 75*58c3e620SPriyanka Jain wriop_set_phy_address(WRIOP1_DPMAC4, 0, 76*58c3e620SPriyanka Jain AQR107_PHY_ADDR2); 77*58c3e620SPriyanka Jain if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) { 78*58c3e620SPriyanka Jain wriop_set_phy_address(WRIOP1_DPMAC5, 0, 79*58c3e620SPriyanka Jain INPHI_PHY_ADDR1); 80*58c3e620SPriyanka Jain wriop_set_phy_address(WRIOP1_DPMAC6, 0, 81*58c3e620SPriyanka Jain INPHI_PHY_ADDR1); 82*58c3e620SPriyanka Jain } 83*58c3e620SPriyanka Jain wriop_set_phy_address(WRIOP1_DPMAC17, 0, 84*58c3e620SPriyanka Jain RGMII_PHY_ADDR1); 85*58c3e620SPriyanka Jain wriop_set_phy_address(WRIOP1_DPMAC18, 0, 86*58c3e620SPriyanka Jain RGMII_PHY_ADDR2); 87*58c3e620SPriyanka Jain break; 88*58c3e620SPriyanka Jain 89*58c3e620SPriyanka Jain case 18: 90*58c3e620SPriyanka Jain wriop_set_phy_address(WRIOP1_DPMAC7, 0, 91*58c3e620SPriyanka Jain CORTINA_PHY_ADDR1); 92*58c3e620SPriyanka Jain wriop_set_phy_address(WRIOP1_DPMAC8, 0, 93*58c3e620SPriyanka Jain CORTINA_PHY_ADDR1); 94*58c3e620SPriyanka Jain wriop_set_phy_address(WRIOP1_DPMAC9, 0, 95*58c3e620SPriyanka Jain CORTINA_PHY_ADDR1); 96*58c3e620SPriyanka Jain wriop_set_phy_address(WRIOP1_DPMAC10, 0, 97*58c3e620SPriyanka Jain CORTINA_PHY_ADDR1); 98*58c3e620SPriyanka Jain wriop_set_phy_address(WRIOP1_DPMAC3, 0, 99*58c3e620SPriyanka Jain AQR107_PHY_ADDR1); 100*58c3e620SPriyanka Jain wriop_set_phy_address(WRIOP1_DPMAC4, 0, 101*58c3e620SPriyanka Jain AQR107_PHY_ADDR2); 102*58c3e620SPriyanka Jain if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) { 103*58c3e620SPriyanka Jain wriop_set_phy_address(WRIOP1_DPMAC5, 0, 104*58c3e620SPriyanka Jain INPHI_PHY_ADDR1); 105*58c3e620SPriyanka Jain wriop_set_phy_address(WRIOP1_DPMAC6, 0, 106*58c3e620SPriyanka Jain INPHI_PHY_ADDR1); 107*58c3e620SPriyanka Jain } 108*58c3e620SPriyanka Jain wriop_set_phy_address(WRIOP1_DPMAC17, 0, 109*58c3e620SPriyanka Jain RGMII_PHY_ADDR1); 110*58c3e620SPriyanka Jain wriop_set_phy_address(WRIOP1_DPMAC18, 0, 111*58c3e620SPriyanka Jain RGMII_PHY_ADDR2); 112*58c3e620SPriyanka Jain break; 113*58c3e620SPriyanka Jain 114*58c3e620SPriyanka Jain default: 115*58c3e620SPriyanka Jain printf("SerDes1 protocol 0x%x is not supported on LX2160ARDB\n", 116*58c3e620SPriyanka Jain srds_s1); 117*58c3e620SPriyanka Jain goto next; 118*58c3e620SPriyanka Jain } 119*58c3e620SPriyanka Jain 120*58c3e620SPriyanka Jain for (i = WRIOP1_DPMAC2; i <= WRIOP1_DPMAC10; i++) { 121*58c3e620SPriyanka Jain interface = wriop_get_enet_if(i); 122*58c3e620SPriyanka Jain switch (interface) { 123*58c3e620SPriyanka Jain case PHY_INTERFACE_MODE_XGMII: 124*58c3e620SPriyanka Jain dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); 125*58c3e620SPriyanka Jain wriop_set_mdio(i, dev); 126*58c3e620SPriyanka Jain break; 127*58c3e620SPriyanka Jain case PHY_INTERFACE_MODE_25G_AUI: 128*58c3e620SPriyanka Jain dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); 129*58c3e620SPriyanka Jain wriop_set_mdio(i, dev); 130*58c3e620SPriyanka Jain break; 131*58c3e620SPriyanka Jain case PHY_INTERFACE_MODE_XLAUI: 132*58c3e620SPriyanka Jain dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); 133*58c3e620SPriyanka Jain wriop_set_mdio(i, dev); 134*58c3e620SPriyanka Jain break; 135*58c3e620SPriyanka Jain default: 136*58c3e620SPriyanka Jain break; 137*58c3e620SPriyanka Jain } 138*58c3e620SPriyanka Jain } 139*58c3e620SPriyanka Jain for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC18; i++) { 140*58c3e620SPriyanka Jain interface = wriop_get_enet_if(i); 141*58c3e620SPriyanka Jain switch (interface) { 142*58c3e620SPriyanka Jain case PHY_INTERFACE_MODE_RGMII: 143*58c3e620SPriyanka Jain case PHY_INTERFACE_MODE_RGMII_ID: 144*58c3e620SPriyanka Jain dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); 145*58c3e620SPriyanka Jain wriop_set_mdio(i, dev); 146*58c3e620SPriyanka Jain break; 147*58c3e620SPriyanka Jain default: 148*58c3e620SPriyanka Jain break; 149*58c3e620SPriyanka Jain } 150*58c3e620SPriyanka Jain } 151*58c3e620SPriyanka Jain 152*58c3e620SPriyanka Jain next: 153*58c3e620SPriyanka Jain cpu_eth_init(bis); 154*58c3e620SPriyanka Jain #endif /* CONFIG_FSL_MC_ENET */ 155*58c3e620SPriyanka Jain 156*58c3e620SPriyanka Jain #ifdef CONFIG_PHY_AQUANTIA 157*58c3e620SPriyanka Jain /* 158*58c3e620SPriyanka Jain * Export functions to be used by AQ firmware 159*58c3e620SPriyanka Jain * upload application 160*58c3e620SPriyanka Jain */ 161*58c3e620SPriyanka Jain gd->jt->strcpy = strcpy; 162*58c3e620SPriyanka Jain gd->jt->mdelay = mdelay; 163*58c3e620SPriyanka Jain gd->jt->mdio_get_current_dev = mdio_get_current_dev; 164*58c3e620SPriyanka Jain gd->jt->phy_find_by_mask = phy_find_by_mask; 165*58c3e620SPriyanka Jain gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; 166*58c3e620SPriyanka Jain gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; 167*58c3e620SPriyanka Jain #endif 168*58c3e620SPriyanka Jain return pci_eth_init(bis); 169*58c3e620SPriyanka Jain } 170*58c3e620SPriyanka Jain 171*58c3e620SPriyanka Jain #if defined(CONFIG_RESET_PHY_R) 172*58c3e620SPriyanka Jain void reset_phy(void) 173*58c3e620SPriyanka Jain { 174*58c3e620SPriyanka Jain #if defined(CONFIG_FSL_MC_ENET) 175*58c3e620SPriyanka Jain mc_env_boot(); 176*58c3e620SPriyanka Jain #endif 177*58c3e620SPriyanka Jain } 178*58c3e620SPriyanka Jain #endif /* CONFIG_RESET_PHY_R */ 179*58c3e620SPriyanka Jain 180*58c3e620SPriyanka Jain int fdt_fixup_board_phy(void *fdt) 181*58c3e620SPriyanka Jain { 182*58c3e620SPriyanka Jain int mdio_offset; 183*58c3e620SPriyanka Jain int ret; 184*58c3e620SPriyanka Jain struct mii_dev *dev; 185*58c3e620SPriyanka Jain 186*58c3e620SPriyanka Jain ret = 0; 187*58c3e620SPriyanka Jain 188*58c3e620SPriyanka Jain dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); 189*58c3e620SPriyanka Jain if (!get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) { 190*58c3e620SPriyanka Jain mdio_offset = fdt_path_offset(fdt, "/soc/mdio@0x8B97000"); 191*58c3e620SPriyanka Jain 192*58c3e620SPriyanka Jain if (mdio_offset < 0) 193*58c3e620SPriyanka Jain mdio_offset = fdt_path_offset(fdt, "/mdio@0x8B97000"); 194*58c3e620SPriyanka Jain 195*58c3e620SPriyanka Jain if (mdio_offset < 0) { 196*58c3e620SPriyanka Jain printf("mdio@0x8B9700 node not found in dts\n"); 197*58c3e620SPriyanka Jain return mdio_offset; 198*58c3e620SPriyanka Jain } 199*58c3e620SPriyanka Jain 200*58c3e620SPriyanka Jain ret = fdt_setprop_string(fdt, mdio_offset, "status", 201*58c3e620SPriyanka Jain "disabled"); 202*58c3e620SPriyanka Jain if (ret) { 203*58c3e620SPriyanka Jain printf("Could not set disable mdio@0x8B97000 %s\n", 204*58c3e620SPriyanka Jain fdt_strerror(ret)); 205*58c3e620SPriyanka Jain return ret; 206*58c3e620SPriyanka Jain } 207*58c3e620SPriyanka Jain } 208*58c3e620SPriyanka Jain 209*58c3e620SPriyanka Jain return ret; 210*58c3e620SPriyanka Jain } 211