1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2018-2019 NXP
4 *
5 */
6
7 #include <common.h>
8 #include <hwconfig.h>
9 #include <command.h>
10 #include <netdev.h>
11 #include <malloc.h>
12 #include <fsl_mdio.h>
13 #include <miiphy.h>
14 #include <phy.h>
15 #include <fm_eth.h>
16 #include <asm/io.h>
17 #include <exports.h>
18 #include <asm/arch/fsl_serdes.h>
19 #include <fsl-mc/fsl_mc.h>
20 #include <fsl-mc/ldpaa_wriop.h>
21
22 #include "../common/qixis.h"
23
24 DECLARE_GLOBAL_DATA_PTR;
25
26 #define EMI_NONE 0
27 #define EMI1 1 /* Mdio Bus 1 */
28 #define EMI2 2 /* Mdio Bus 2 */
29
30 #if defined(CONFIG_FSL_MC_ENET)
31 enum io_slot {
32 IO_SLOT_NONE = 0,
33 IO_SLOT_1,
34 IO_SLOT_2,
35 IO_SLOT_3,
36 IO_SLOT_4,
37 IO_SLOT_5,
38 IO_SLOT_6,
39 IO_SLOT_7,
40 IO_SLOT_8,
41 EMI1_RGMII1,
42 EMI1_RGMII2,
43 IO_SLOT_MAX
44 };
45
46 struct lx2160a_qds_mdio {
47 enum io_slot ioslot : 4;
48 u8 realbusnum : 4;
49 struct mii_dev *realbus;
50 };
51
52 /* structure explaining the phy configuration on 8 lanes of a serdes*/
53 struct serdes_phy_config {
54 u8 serdes; /* serdes protocol */
55 struct phy_config {
56 u8 dpmacid;
57 /* -1 terminated array */
58 int phy_address[WRIOP_MAX_PHY_NUM + 1];
59 u8 mdio_bus;
60 enum io_slot ioslot;
61 } phy_config[SRDS_MAX_LANES];
62 };
63
64 /* Table defining the phy configuration on 8 lanes of a serdes.
65 * Various assumptions have been made while defining this table.
66 * e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII
67 * card is being used for dpmac 3-4. (X-M12-XFI could also have been used)
68 * And also that this card is connected to IO Slot 1 (could have been connected
69 * to any of the 8 IO slots (IO slot 1 - IO slot 8)).
70 * similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card
71 * used in serdes1 protocol 19 (could have selected MDIO 2)
72 * To override these settings "dpmac" environment variable can be used after
73 * defining "dpmac_override" in hwconfig environment variable.
74 * This table has limited serdes protocol entries. It can be expanded as per
75 * requirement.
76 */
77 static const struct serdes_phy_config serdes1_phy_config[] = {
78 {3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
79 EMI1, IO_SLOT_1},
80 {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
81 EMI1, IO_SLOT_1},
82 {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
83 EMI1, IO_SLOT_1},
84 {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
85 EMI1, IO_SLOT_1} } },
86 {7, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
87 EMI1, IO_SLOT_1},
88 {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
89 EMI1, IO_SLOT_1},
90 {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
91 EMI1, IO_SLOT_1},
92 {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
93 EMI1, IO_SLOT_1},
94 {WRIOP1_DPMAC7, {SGMII_CARD_PORT1_PHY_ADDR, -1},
95 EMI1, IO_SLOT_2},
96 {WRIOP1_DPMAC8, {SGMII_CARD_PORT2_PHY_ADDR, -1},
97 EMI1, IO_SLOT_2},
98 {WRIOP1_DPMAC9, {SGMII_CARD_PORT3_PHY_ADDR, -1},
99 EMI1, IO_SLOT_2},
100 {WRIOP1_DPMAC10, {SGMII_CARD_PORT4_PHY_ADDR, -1},
101 EMI1, IO_SLOT_2} } },
102 {8, {} },
103 {13, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
104 EMI1, IO_SLOT_1},
105 {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
106 EMI1, IO_SLOT_2} } },
107 {15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
108 EMI1, IO_SLOT_1},
109 {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
110 EMI1, IO_SLOT_1} } },
111 {17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
112 EMI1, IO_SLOT_1},
113 {WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
114 EMI1, IO_SLOT_1},
115 {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
116 EMI1, IO_SLOT_1},
117 {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
118 EMI1, IO_SLOT_1} } },
119 {19, {{WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
120 EMI1, IO_SLOT_2},
121 {WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
122 EMI1, IO_SLOT_1},
123 {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
124 EMI1, IO_SLOT_1},
125 {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
126 EMI1, IO_SLOT_6},
127 {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
128 EMI1, IO_SLOT_6} } },
129 {20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1},
130 EMI1, IO_SLOT_1},
131 {WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
132 EMI1, IO_SLOT_2} } }
133 };
134
135 static const struct serdes_phy_config serdes2_phy_config[] = {
136 {2, {} },
137 {3, {} },
138 {5, {} },
139 {11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
140 EMI1, IO_SLOT_7},
141 {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
142 EMI1, IO_SLOT_7},
143 {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
144 EMI1, IO_SLOT_7},
145 {WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1},
146 EMI1, IO_SLOT_8},
147 {WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1},
148 EMI1, IO_SLOT_8},
149 {WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1},
150 EMI1, IO_SLOT_8} } },
151 };
152
153 static const struct serdes_phy_config serdes3_phy_config[] = {
154 {2, {} },
155 {3, {} }
156 };
157
158 static inline
get_phy_config(u8 serdes,const struct serdes_phy_config * table,u8 table_size)159 const struct phy_config *get_phy_config(u8 serdes,
160 const struct serdes_phy_config *table,
161 u8 table_size)
162 {
163 int i;
164
165 for (i = 0; i < table_size; i++) {
166 if (table[i].serdes == serdes)
167 return table[i].phy_config;
168 }
169
170 return NULL;
171 }
172
173 /* BRDCFG4 controls EMI routing for the board.
174 * Bits Function
175 * 7-6 EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V):
176 * EMI1 00= On-board PHY #1
177 * 01= On-board PHY #2
178 * 10= (reserved)
179 * 11= Slots 1..8 multiplexer and translator.
180 * 5-3 EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V):
181 * EMI1X 000= Slot #1
182 * 001= Slot #2
183 * 010= Slot #3
184 * 011= Slot #4
185 * 100= Slot #5
186 * 101= Slot #6
187 * 110= Slot #7
188 * 111= Slot #8
189 * 2-0 EMI Interface #2 Routing (CFG_MUX_EMI2):
190 * EMI2 000= Slot #1 (secondary EMI)
191 * 001= Slot #2 (secondary EMI)
192 * 010= Slot #3 (secondary EMI)
193 * 011= Slot #4 (secondary EMI)
194 * 100= Slot #5 (secondary EMI)
195 * 101= Slot #6 (secondary EMI)
196 * 110= Slot #7 (secondary EMI)
197 * 111= Slot #8 (secondary EMI)
198 */
lx2160a_qds_get_mdio_mux_val(u8 realbusnum,enum io_slot ioslot)199 static int lx2160a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot ioslot)
200 {
201 switch (realbusnum) {
202 case EMI1:
203 switch (ioslot) {
204 case EMI1_RGMII1:
205 return 0;
206 case EMI1_RGMII2:
207 return 0x40;
208 default:
209 return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) | 0xC0);
210 }
211 break;
212 case EMI2:
213 return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT);
214 default:
215 return -1;
216 }
217 }
218
lx2160a_qds_mux_mdio(struct lx2160a_qds_mdio * priv)219 static void lx2160a_qds_mux_mdio(struct lx2160a_qds_mdio *priv)
220 {
221 u8 brdcfg4, mux_val, reg;
222
223 brdcfg4 = QIXIS_READ(brdcfg[4]);
224 reg = brdcfg4;
225 mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
226
227 switch (priv->realbusnum) {
228 case EMI1:
229 brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK;
230 brdcfg4 |= mux_val;
231 break;
232 case EMI2:
233 brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK;
234 brdcfg4 |= mux_val;
235 break;
236 }
237
238 if (brdcfg4 ^ reg)
239 QIXIS_WRITE(brdcfg[4], brdcfg4);
240 }
241
lx2160a_qds_mdio_read(struct mii_dev * bus,int addr,int devad,int regnum)242 static int lx2160a_qds_mdio_read(struct mii_dev *bus, int addr,
243 int devad, int regnum)
244 {
245 struct lx2160a_qds_mdio *priv = bus->priv;
246
247 lx2160a_qds_mux_mdio(priv);
248
249 return priv->realbus->read(priv->realbus, addr, devad, regnum);
250 }
251
lx2160a_qds_mdio_write(struct mii_dev * bus,int addr,int devad,int regnum,u16 value)252 static int lx2160a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
253 int regnum, u16 value)
254 {
255 struct lx2160a_qds_mdio *priv = bus->priv;
256
257 lx2160a_qds_mux_mdio(priv);
258
259 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
260 }
261
lx2160a_qds_mdio_reset(struct mii_dev * bus)262 static int lx2160a_qds_mdio_reset(struct mii_dev *bus)
263 {
264 struct lx2160a_qds_mdio *priv = bus->priv;
265
266 return priv->realbus->reset(priv->realbus);
267 }
268
lx2160a_qds_mdio_init(u8 realbusnum,enum io_slot ioslot)269 static struct mii_dev *lx2160a_qds_mdio_init(u8 realbusnum, enum io_slot ioslot)
270 {
271 struct lx2160a_qds_mdio *pmdio;
272 struct mii_dev *bus;
273 /*should be within MDIO_NAME_LEN*/
274 char dummy_mdio_name[] = "LX2160A_QDS_MDIO1_IOSLOT1";
275
276 if (realbusnum == EMI2) {
277 if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) {
278 printf("invalid ioslot %d\n", ioslot);
279 return NULL;
280 }
281 } else if (realbusnum == EMI1) {
282 if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) {
283 printf("invalid ioslot %d\n", ioslot);
284 return NULL;
285 }
286 } else {
287 printf("not supported real mdio bus %d\n", realbusnum);
288 return NULL;
289 }
290
291 if (ioslot == EMI1_RGMII1)
292 strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII1");
293 else if (ioslot == EMI1_RGMII2)
294 strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII2");
295 else
296 sprintf(dummy_mdio_name, "LX2160A_QDS_MDIO%d_IOSLOT%d",
297 realbusnum, ioslot);
298 bus = miiphy_get_dev_by_name(dummy_mdio_name);
299
300 if (bus)
301 return bus;
302
303 bus = mdio_alloc();
304 if (!bus) {
305 printf("Failed to allocate %s bus\n", dummy_mdio_name);
306 return NULL;
307 }
308
309 pmdio = malloc(sizeof(*pmdio));
310 if (!pmdio) {
311 printf("Failed to allocate %s private data\n", dummy_mdio_name);
312 free(bus);
313 return NULL;
314 }
315
316 switch (realbusnum) {
317 case EMI1:
318 pmdio->realbus =
319 miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
320 break;
321 case EMI2:
322 pmdio->realbus =
323 miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
324 break;
325 }
326
327 if (!pmdio->realbus) {
328 printf("No real mdio bus num %d found\n", realbusnum);
329 free(bus);
330 free(pmdio);
331 return NULL;
332 }
333
334 pmdio->realbusnum = realbusnum;
335 pmdio->ioslot = ioslot;
336 bus->read = lx2160a_qds_mdio_read;
337 bus->write = lx2160a_qds_mdio_write;
338 bus->reset = lx2160a_qds_mdio_reset;
339 strcpy(bus->name, dummy_mdio_name);
340 bus->priv = pmdio;
341
342 if (!mdio_register(bus))
343 return bus;
344
345 printf("No bus with name %s\n", dummy_mdio_name);
346 free(bus);
347 free(pmdio);
348 return NULL;
349 }
350
do_phy_config(const struct phy_config * phy_config)351 static inline void do_phy_config(const struct phy_config *phy_config)
352 {
353 struct mii_dev *bus;
354 int i, phy_num, phy_address;
355
356 for (i = 0; i < SRDS_MAX_LANES; i++) {
357 if (!phy_config[i].dpmacid)
358 continue;
359
360 for (phy_num = 0;
361 phy_num < ARRAY_SIZE(phy_config[i].phy_address);
362 phy_num++) {
363 phy_address = phy_config[i].phy_address[phy_num];
364 if (phy_address == -1)
365 break;
366 wriop_set_phy_address(phy_config[i].dpmacid,
367 phy_num, phy_address);
368 }
369 /*Register the muxing front-ends to the MDIO buses*/
370 bus = lx2160a_qds_mdio_init(phy_config[i].mdio_bus,
371 phy_config[i].ioslot);
372 if (!bus)
373 printf("could not get bus for mdio %d ioslot %d\n",
374 phy_config[i].mdio_bus,
375 phy_config[i].ioslot);
376 else
377 wriop_set_mdio(phy_config[i].dpmacid, bus);
378 }
379 }
380
do_dpmac_config(int dpmac,const char * arg_dpmacid,char * env_dpmac)381 static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid,
382 char *env_dpmac)
383 {
384 const char *ret;
385 size_t len;
386 u8 realbusnum, ioslot;
387 struct mii_dev *bus;
388 int phy_num;
389 char *phystr = "phy00";
390
391 /*search phy in dpmac arg*/
392 for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
393 sprintf(phystr, "phy%d", phy_num + 1);
394 ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len, env_dpmac);
395 if (!ret) {
396 /*look for phy instead of phy1*/
397 if (!phy_num)
398 ret = hwconfig_subarg_f(arg_dpmacid, "phy",
399 &len, env_dpmac);
400 if (!ret)
401 continue;
402 }
403
404 if (len != 4 || strncmp(ret, "0x", 2))
405 printf("invalid phy format in %s variable.\n"
406 "specify phy%d for %s in hex format e.g. 0x12\n",
407 env_dpmac, phy_num + 1, arg_dpmacid);
408 else
409 wriop_set_phy_address(dpmac, phy_num,
410 simple_strtoul(ret, NULL, 16));
411 }
412
413 /*search mdio in dpmac arg*/
414 ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac);
415 if (ret)
416 realbusnum = *ret - '0';
417 else
418 realbusnum = EMI_NONE;
419
420 if (realbusnum) {
421 /*search io in dpmac arg*/
422 ret = hwconfig_subarg_f(arg_dpmacid, "io", &len, env_dpmac);
423 if (ret)
424 ioslot = *ret - '0';
425 else
426 ioslot = IO_SLOT_NONE;
427 /*Register the muxing front-ends to the MDIO buses*/
428 bus = lx2160a_qds_mdio_init(realbusnum, ioslot);
429 if (!bus)
430 printf("could not get bus for mdio %d ioslot %d\n",
431 realbusnum, ioslot);
432 else
433 wriop_set_mdio(dpmac, bus);
434 }
435 }
436
437 #endif
438
board_eth_init(bd_t * bis)439 int board_eth_init(bd_t *bis)
440 {
441 #if defined(CONFIG_FSL_MC_ENET)
442 struct memac_mdio_info mdio_info;
443 struct memac_mdio_controller *regs;
444 int i;
445 const char *ret;
446 char *env_dpmac;
447 char dpmacid[] = "dpmac00", srds[] = "00_00_00";
448 size_t len;
449 struct mii_dev *bus;
450 const struct phy_config *phy_config;
451 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
452 u32 srds_s1, srds_s2, srds_s3;
453
454 srds_s1 = in_le32(&gur->rcwsr[28]) &
455 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
456 srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
457
458 srds_s2 = in_le32(&gur->rcwsr[28]) &
459 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
460 srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
461
462 srds_s3 = in_le32(&gur->rcwsr[28]) &
463 FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK;
464 srds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT;
465
466 sprintf(srds, "%d_%d_%d", srds_s1, srds_s2, srds_s3);
467
468 regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
469 mdio_info.regs = regs;
470 mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
471
472 /*Register the EMI 1*/
473 fm_memac_mdio_init(bis, &mdio_info);
474
475 regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
476 mdio_info.regs = regs;
477 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
478
479 /*Register the EMI 2*/
480 fm_memac_mdio_init(bis, &mdio_info);
481
482 /* "dpmac" environment variable can be used after
483 * defining "dpmac_override" in hwconfig environment variable.
484 */
485 if (hwconfig("dpmac_override")) {
486 env_dpmac = env_get("dpmac");
487 if (env_dpmac) {
488 ret = hwconfig_arg_f("srds", &len, env_dpmac);
489 if (ret) {
490 if (strncmp(ret, srds, strlen(srds))) {
491 printf("SERDES configuration changed.\n"
492 "previous: %.*s, current: %s.\n"
493 "update dpmac variable.\n",
494 (int)len, ret, srds);
495 }
496 } else {
497 printf("SERDES configuration not found.\n"
498 "Please add srds:%s in dpmac variable\n",
499 srds);
500 }
501
502 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
503 /* Look for dpmac1 to dpmac24(current max) arg
504 * in dpmac environment variable
505 */
506 sprintf(dpmacid, "dpmac%d", i);
507 ret = hwconfig_arg_f(dpmacid, &len, env_dpmac);
508 if (ret)
509 do_dpmac_config(i, dpmacid, env_dpmac);
510 }
511 } else {
512 printf("Warning: environment dpmac not found.\n"
513 "DPAA network interfaces may not work\n");
514 }
515 } else {
516 /*Look for phy config for serdes1 in phy config table*/
517 phy_config = get_phy_config(srds_s1, serdes1_phy_config,
518 ARRAY_SIZE(serdes1_phy_config));
519 if (!phy_config) {
520 printf("%s WRIOP: Unsupported SerDes1 Protocol %d\n",
521 __func__, srds_s1);
522 } else {
523 do_phy_config(phy_config);
524 }
525 phy_config = get_phy_config(srds_s2, serdes2_phy_config,
526 ARRAY_SIZE(serdes2_phy_config));
527 if (!phy_config) {
528 printf("%s WRIOP: Unsupported SerDes2 Protocol %d\n",
529 __func__, srds_s2);
530 } else {
531 do_phy_config(phy_config);
532 }
533 phy_config = get_phy_config(srds_s3, serdes3_phy_config,
534 ARRAY_SIZE(serdes3_phy_config));
535 if (!phy_config) {
536 printf("%s WRIOP: Unsupported SerDes3 Protocol %d\n",
537 __func__, srds_s3);
538 } else {
539 do_phy_config(phy_config);
540 }
541 }
542
543 if (wriop_get_enet_if(WRIOP1_DPMAC17) == PHY_INTERFACE_MODE_RGMII_ID) {
544 wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1);
545 bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII1);
546 if (!bus)
547 printf("could not get bus for RGMII1\n");
548 else
549 wriop_set_mdio(WRIOP1_DPMAC17, bus);
550 }
551
552 if (wriop_get_enet_if(WRIOP1_DPMAC18) == PHY_INTERFACE_MODE_RGMII_ID) {
553 wriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2);
554 bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII2);
555 if (!bus)
556 printf("could not get bus for RGMII2\n");
557 else
558 wriop_set_mdio(WRIOP1_DPMAC18, bus);
559 }
560
561 cpu_eth_init(bis);
562 #endif /* CONFIG_FMAN_ENET */
563
564 #ifdef CONFIG_PHY_AQUANTIA
565 /*
566 * Export functions to be used by AQ firmware
567 * upload application
568 */
569 gd->jt->strcpy = strcpy;
570 gd->jt->mdelay = mdelay;
571 gd->jt->mdio_get_current_dev = mdio_get_current_dev;
572 gd->jt->phy_find_by_mask = phy_find_by_mask;
573 gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
574 gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
575 #endif
576 return pci_eth_init(bis);
577 }
578
579 #if defined(CONFIG_RESET_PHY_R)
reset_phy(void)580 void reset_phy(void)
581 {
582 #if defined(CONFIG_FSL_MC_ENET)
583 mc_env_boot();
584 #endif
585 }
586 #endif /* CONFIG_RESET_PHY_R */
587
588 #if defined(CONFIG_FSL_MC_ENET)
fdt_fixup_dpmac_phy_handle(void * fdt,int dpmac_id,int node_phandle)589 int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
590 {
591 int offset;
592 int ret;
593 char dpmac_str[] = "dpmacs@00";
594 const char *phy_string;
595
596 offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs");
597
598 if (offset < 0)
599 offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs");
600
601 if (offset < 0) {
602 printf("dpmacs node not found in device tree\n");
603 return offset;
604 }
605
606 sprintf(dpmac_str, "dpmac@%x", dpmac_id);
607 debug("dpmac_str = %s\n", dpmac_str);
608
609 offset = fdt_subnode_offset(fdt, offset, dpmac_str);
610 if (offset < 0) {
611 printf("%s node not found in device tree\n", dpmac_str);
612 return offset;
613 }
614
615 ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle);
616 if (ret)
617 printf("%d@%s %d\n", __LINE__, __func__, ret);
618
619 phy_string = phy_string_for_interface(wriop_get_enet_if(dpmac_id));
620 ret = fdt_setprop_string(fdt, offset, "phy-connection-type",
621 phy_string);
622 if (ret)
623 printf("%d@%s %d\n", __LINE__, __func__, ret);
624
625 return ret;
626 }
627
fdt_get_ioslot_offset(void * fdt,struct mii_dev * mii_dev,int fpga_offset)628 int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
629 {
630 char mdio_ioslot_str[] = "mdio@00";
631 struct lx2160a_qds_mdio *priv;
632 u64 reg;
633 u32 phandle;
634 int offset, mux_val;
635
636 /*Test if the MDIO bus is real mdio bus or muxing front end ?*/
637 if (strncmp(mii_dev->name, "LX2160A_QDS_MDIO",
638 strlen("LX2160A_QDS_MDIO")))
639 return -1;
640
641 /*Get the real MDIO bus num and ioslot info from bus's priv data*/
642 priv = mii_dev->priv;
643
644 debug("real_bus_num = %d, ioslot = %d\n",
645 priv->realbusnum, priv->ioslot);
646
647 if (priv->realbusnum == EMI1)
648 reg = CONFIG_SYS_FSL_WRIOP1_MDIO1;
649 else
650 reg = CONFIG_SYS_FSL_WRIOP1_MDIO2;
651
652 offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
653 if (offset < 0) {
654 printf("mdio@%llx node not found in device tree\n", reg);
655 return offset;
656 }
657
658 phandle = fdt_get_phandle(fdt, offset);
659 phandle = cpu_to_fdt32(phandle);
660 offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus",
661 &phandle, 4);
662 if (offset < 0) {
663 printf("mdio-mux-%d node not found in device tree\n",
664 priv->realbusnum == EMI1 ? 1 : 2);
665 return offset;
666 }
667
668 mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
669 if (priv->realbusnum == EMI1)
670 mux_val >>= BRDCFG4_EMI1SEL_SHIFT;
671 else
672 mux_val >>= BRDCFG4_EMI2SEL_SHIFT;
673 sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
674
675 offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
676 if (offset < 0) {
677 printf("%s node not found in device tree\n", mdio_ioslot_str);
678 return offset;
679 }
680
681 return offset;
682 }
683
fdt_create_phy_node(void * fdt,int offset,u8 phyaddr,int * subnodeoffset,struct phy_device * phy_dev,int phandle)684 int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
685 struct phy_device *phy_dev, int phandle)
686 {
687 char phy_node_name[] = "ethernet-phy@00";
688 char phy_id_compatible_str[] = "ethernet-phy-id0000.0000";
689 int ret;
690
691 sprintf(phy_node_name, "ethernet-phy@%x", phyaddr);
692 debug("phy_node_name = %s\n", phy_node_name);
693
694 *subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
695 if (*subnodeoffset <= 0) {
696 printf("Could not add subnode %s inside node %s err = %s\n",
697 phy_node_name, fdt_get_name(fdt, offset, NULL),
698 fdt_strerror(*subnodeoffset));
699 return *subnodeoffset;
700 }
701
702 sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x",
703 phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF);
704 debug("phy_id_compatible_str %s\n", phy_id_compatible_str);
705
706 ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible",
707 phy_id_compatible_str);
708 if (ret) {
709 printf("%d@%s %d\n", __LINE__, __func__, ret);
710 goto out;
711 }
712
713 if (phy_dev->is_c45) {
714 ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
715 "ethernet-phy-ieee802.3-c45");
716 if (ret) {
717 printf("%d@%s %d\n", __LINE__, __func__, ret);
718 goto out;
719 }
720 } else {
721 ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
722 "ethernet-phy-ieee802.3-c22");
723 if (ret) {
724 printf("%d@%s %d\n", __LINE__, __func__, ret);
725 goto out;
726 }
727 }
728
729 ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr);
730 if (ret) {
731 printf("%d@%s %d\n", __LINE__, __func__, ret);
732 goto out;
733 }
734
735 ret = fdt_set_phandle(fdt, *subnodeoffset, phandle);
736 if (ret) {
737 printf("%d@%s %d\n", __LINE__, __func__, ret);
738 goto out;
739 }
740
741 out:
742 if (ret)
743 fdt_del_node(fdt, *subnodeoffset);
744
745 return ret;
746 }
747
fdt_fixup_board_phy(void * fdt)748 int fdt_fixup_board_phy(void *fdt)
749 {
750 int fpga_offset, offset, subnodeoffset;
751 struct mii_dev *mii_dev;
752 struct list_head *mii_devs, *entry;
753 int ret, dpmac_id, phandle, i;
754 struct phy_device *phy_dev;
755 char ethname[ETH_NAME_LEN];
756 phy_interface_t phy_iface;
757
758 ret = 0;
759 /* we know FPGA is connected to i2c0, therefore search path directly,
760 * instead of compatible property, as it saves time
761 */
762 fpga_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/fpga");
763
764 if (fpga_offset < 0)
765 fpga_offset = fdt_path_offset(fdt, "/i2c@2000000/fpga");
766
767 if (fpga_offset < 0) {
768 printf("i2c@2000000/fpga node not found in device tree\n");
769 return fpga_offset;
770 }
771
772 phandle = fdt_alloc_phandle(fdt);
773 mii_devs = mdio_get_list_head();
774
775 list_for_each(entry, mii_devs) {
776 mii_dev = list_entry(entry, struct mii_dev, link);
777 debug("mii_dev name : %s\n", mii_dev->name);
778 offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset);
779 if (offset < 0)
780 continue;
781
782 // Look for phy devices attached to MDIO bus muxing front end
783 // and create their entries with compatible being the device id
784 for (i = 0; i < PHY_MAX_ADDR; i++) {
785 phy_dev = mii_dev->phymap[i];
786 if (!phy_dev)
787 continue;
788
789 // TODO: use sscanf instead of loop
790 dpmac_id = WRIOP1_DPMAC1;
791 while (dpmac_id < NUM_WRIOP_PORTS) {
792 phy_iface = wriop_get_enet_if(dpmac_id);
793 snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s",
794 dpmac_id,
795 phy_string_for_interface(phy_iface));
796 if (strcmp(ethname, phy_dev->dev->name) == 0)
797 break;
798 dpmac_id++;
799 }
800 if (dpmac_id == NUM_WRIOP_PORTS)
801 continue;
802 ret = fdt_create_phy_node(fdt, offset, i,
803 &subnodeoffset,
804 phy_dev, phandle);
805 if (ret)
806 break;
807
808 ret = fdt_fixup_dpmac_phy_handle(fdt,
809 dpmac_id, phandle);
810 if (ret) {
811 fdt_del_node(fdt, subnodeoffset);
812 break;
813 }
814 /* calculate offset again as new node addition may have
815 * changed offset;
816 */
817 offset = fdt_get_ioslot_offset(fdt, mii_dev,
818 fpga_offset);
819 phandle++;
820 }
821
822 if (ret)
823 break;
824 }
825
826 return ret;
827 }
828 #endif // CONFIG_FSL_MC_ENET
829
830