1 /* 2 * Copyright (C) 2017 NXP Semiconductors 3 * Copyright 2015 Freescale Semiconductor 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 #include <common.h> 8 #include <malloc.h> 9 #include <errno.h> 10 #include <netdev.h> 11 #include <fsl_ifc.h> 12 #include <fsl_ddr.h> 13 #include <asm/io.h> 14 #include <hwconfig.h> 15 #include <fdt_support.h> 16 #include <libfdt.h> 17 #include <fsl-mc/fsl_mc.h> 18 #include <environment.h> 19 #include <efi_loader.h> 20 #include <i2c.h> 21 #include <asm/arch/mmu.h> 22 #include <asm/arch/soc.h> 23 #include <asm/arch/ppa.h> 24 #include <fsl_sec.h> 25 26 #ifdef CONFIG_FSL_QIXIS 27 #include "../common/qixis.h" 28 #include "ls2080ardb_qixis.h" 29 #endif 30 #include "../common/vid.h" 31 32 #define PIN_MUX_SEL_SDHC 0x00 33 #define PIN_MUX_SEL_DSPI 0x0a 34 35 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value) 36 DECLARE_GLOBAL_DATA_PTR; 37 38 enum { 39 MUX_TYPE_SDHC, 40 MUX_TYPE_DSPI, 41 }; 42 43 unsigned long long get_qixis_addr(void) 44 { 45 unsigned long long addr; 46 47 if (gd->flags & GD_FLG_RELOC) 48 addr = QIXIS_BASE_PHYS; 49 else 50 addr = QIXIS_BASE_PHYS_EARLY; 51 52 /* 53 * IFC address under 256MB is mapped to 0x30000000, any address above 54 * is mapped to 0x5_10000000 up to 4GB. 55 */ 56 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; 57 58 return addr; 59 } 60 61 int checkboard(void) 62 { 63 #ifdef CONFIG_FSL_QIXIS 64 u8 sw; 65 #endif 66 char buf[15]; 67 68 cpu_name(buf); 69 printf("Board: %s-RDB, ", buf); 70 71 #ifdef CONFIG_TARGET_LS2081ARDB 72 #ifdef CONFIG_FSL_QIXIS 73 sw = QIXIS_READ(arch); 74 printf("Board Arch: V%d, ", sw >> 4); 75 printf("Board version: %c, ", (sw & 0xf) + 'A'); 76 77 sw = QIXIS_READ(brdcfg[0]); 78 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT; 79 switch (sw) { 80 case 0: 81 puts("boot from QSPI DEV#0\n"); 82 puts("QSPI_CSA_1 mapped to QSPI DEV#1\n"); 83 break; 84 case 1: 85 puts("boot from QSPI DEV#1\n"); 86 puts("QSPI_CSA_1 mapped to QSPI DEV#0\n"); 87 break; 88 case 2: 89 puts("boot from QSPI EMU\n"); 90 puts("QSPI_CSA_1 mapped to QSPI DEV#0\n"); 91 break; 92 case 3: 93 puts("boot from QSPI EMU\n"); 94 puts("QSPI_CSA_1 mapped to QSPI DEV#1\n"); 95 break; 96 case 4: 97 puts("boot from QSPI DEV#0\n"); 98 puts("QSPI_CSA_1 mapped to QSPI EMU\n"); 99 break; 100 default: 101 printf("invalid setting of SW%u\n", sw); 102 break; 103 } 104 #endif 105 puts("SERDES1 Reference : "); 106 printf("Clock1 = 100MHz "); 107 printf("Clock2 = 161.13MHz"); 108 #else 109 #ifdef CONFIG_FSL_QIXIS 110 sw = QIXIS_READ(arch); 111 printf("Board Arch: V%d, ", sw >> 4); 112 printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); 113 114 sw = QIXIS_READ(brdcfg[0]); 115 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 116 117 if (sw < 0x8) 118 printf("vBank: %d\n", sw); 119 else if (sw == 0x9) 120 puts("NAND\n"); 121 else 122 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 123 124 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); 125 #endif 126 puts("SERDES1 Reference : "); 127 printf("Clock1 = 156.25MHz "); 128 printf("Clock2 = 156.25MHz"); 129 #endif 130 131 puts("\nSERDES2 Reference : "); 132 printf("Clock1 = 100MHz "); 133 printf("Clock2 = 100MHz\n"); 134 135 return 0; 136 } 137 138 unsigned long get_board_sys_clk(void) 139 { 140 #ifdef CONFIG_FSL_QIXIS 141 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 142 143 switch (sysclk_conf & 0x0F) { 144 case QIXIS_SYSCLK_83: 145 return 83333333; 146 case QIXIS_SYSCLK_100: 147 return 100000000; 148 case QIXIS_SYSCLK_125: 149 return 125000000; 150 case QIXIS_SYSCLK_133: 151 return 133333333; 152 case QIXIS_SYSCLK_150: 153 return 150000000; 154 case QIXIS_SYSCLK_160: 155 return 160000000; 156 case QIXIS_SYSCLK_166: 157 return 166666666; 158 } 159 #endif 160 return 100000000; 161 } 162 163 int select_i2c_ch_pca9547(u8 ch) 164 { 165 int ret; 166 167 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 168 if (ret) { 169 puts("PCA: failed to select proper channel\n"); 170 return ret; 171 } 172 173 return 0; 174 } 175 176 int i2c_multiplexer_select_vid_channel(u8 channel) 177 { 178 return select_i2c_ch_pca9547(channel); 179 } 180 181 int config_board_mux(int ctrl_type) 182 { 183 #ifdef CONFIG_FSL_QIXIS 184 u8 reg5; 185 186 reg5 = QIXIS_READ(brdcfg[5]); 187 188 switch (ctrl_type) { 189 case MUX_TYPE_SDHC: 190 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC); 191 break; 192 case MUX_TYPE_DSPI: 193 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI); 194 break; 195 default: 196 printf("Wrong mux interface type\n"); 197 return -1; 198 } 199 200 QIXIS_WRITE(brdcfg[5], reg5); 201 #endif 202 return 0; 203 } 204 205 int board_init(void) 206 { 207 #ifdef CONFIG_FSL_MC_ENET 208 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; 209 #endif 210 211 init_final_memctl_regs(); 212 213 #ifdef CONFIG_ENV_IS_NOWHERE 214 gd->env_addr = (ulong)&default_environment[0]; 215 #endif 216 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 217 218 #ifdef CONFIG_FSL_QIXIS 219 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); 220 #endif 221 #ifdef CONFIG_FSL_LS_PPA 222 ppa_init(); 223 #endif 224 225 #ifdef CONFIG_FSL_MC_ENET 226 /* invert AQR405 IRQ pins polarity */ 227 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); 228 #endif 229 #ifdef CONFIG_FSL_CAAM 230 sec_init(); 231 #endif 232 233 return 0; 234 } 235 236 int board_early_init_f(void) 237 { 238 #ifdef CONFIG_SYS_I2C_EARLY_INIT 239 i2c_early_init_f(); 240 #endif 241 fsl_lsch3_early_init_f(); 242 return 0; 243 } 244 245 int misc_init_r(void) 246 { 247 char *env_hwconfig; 248 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; 249 u32 val; 250 251 val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4); 252 253 env_hwconfig = getenv("hwconfig"); 254 255 if (hwconfig_f("dspi", env_hwconfig) && 256 DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8))) 257 config_board_mux(MUX_TYPE_DSPI); 258 else 259 config_board_mux(MUX_TYPE_SDHC); 260 261 /* 262 * LS2081ARDB RevF board has smart voltage translator 263 * which needs to be programmed to enable high speed SD interface 264 * by setting GPIO4_10 output to zero 265 */ 266 #ifdef CONFIG_TARGET_LS2081ARDB 267 out_le32(GPIO4_GPDIR_ADDR, (1 << 21 | 268 in_le32(GPIO4_GPDIR_ADDR))); 269 out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) & 270 in_le32(GPIO4_GPDAT_ADDR))); 271 #endif 272 if (hwconfig("sdhc")) 273 config_board_mux(MUX_TYPE_SDHC); 274 275 if (adjust_vdd(0)) 276 printf("Warning: Adjusting core voltage failed.\n"); 277 278 return 0; 279 } 280 281 void detail_board_ddr_info(void) 282 { 283 puts("\nDDR "); 284 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); 285 print_ddr_info(0); 286 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 287 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { 288 puts("\nDP-DDR "); 289 print_size(gd->bd->bi_dram[2].size, ""); 290 print_ddr_info(CONFIG_DP_DDR_CTRL); 291 } 292 #endif 293 } 294 295 #if defined(CONFIG_ARCH_MISC_INIT) 296 int arch_misc_init(void) 297 { 298 return 0; 299 } 300 #endif 301 302 #ifdef CONFIG_FSL_MC_ENET 303 void fdt_fixup_board_enet(void *fdt) 304 { 305 int offset; 306 307 offset = fdt_path_offset(fdt, "/soc/fsl-mc"); 308 309 if (offset < 0) 310 offset = fdt_path_offset(fdt, "/fsl-mc"); 311 312 if (offset < 0) { 313 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", 314 __func__, offset); 315 return; 316 } 317 318 if (get_mc_boot_status() == 0) 319 fdt_status_okay(fdt, offset); 320 else 321 fdt_status_fail(fdt, offset); 322 } 323 324 void board_quiesce_devices(void) 325 { 326 fsl_mc_ldpaa_exit(gd->bd); 327 } 328 #endif 329 330 #ifdef CONFIG_OF_BOARD_SETUP 331 void fsl_fdt_fixup_flash(void *fdt) 332 { 333 int offset; 334 335 /* 336 * IFC and QSPI are muxed on board. 337 * So disable IFC node in dts if QSPI is enabled or 338 * disable QSPI node in dts in case QSPI is not enabled. 339 */ 340 #ifdef CONFIG_FSL_QSPI 341 offset = fdt_path_offset(fdt, "/soc/ifc"); 342 343 if (offset < 0) 344 offset = fdt_path_offset(fdt, "/ifc"); 345 #else 346 offset = fdt_path_offset(fdt, "/soc/quadspi"); 347 348 if (offset < 0) 349 offset = fdt_path_offset(fdt, "/quadspi"); 350 #endif 351 if (offset < 0) 352 return; 353 354 fdt_status_disabled(fdt, offset); 355 } 356 357 int ft_board_setup(void *blob, bd_t *bd) 358 { 359 u64 base[CONFIG_NR_DRAM_BANKS]; 360 u64 size[CONFIG_NR_DRAM_BANKS]; 361 362 ft_cpu_setup(blob, bd); 363 364 /* fixup DT for the two GPP DDR banks */ 365 base[0] = gd->bd->bi_dram[0].start; 366 size[0] = gd->bd->bi_dram[0].size; 367 base[1] = gd->bd->bi_dram[1].start; 368 size[1] = gd->bd->bi_dram[1].size; 369 370 #ifdef CONFIG_RESV_RAM 371 /* reduce size if reserved memory is within this bank */ 372 if (gd->arch.resv_ram >= base[0] && 373 gd->arch.resv_ram < base[0] + size[0]) 374 size[0] = gd->arch.resv_ram - base[0]; 375 else if (gd->arch.resv_ram >= base[1] && 376 gd->arch.resv_ram < base[1] + size[1]) 377 size[1] = gd->arch.resv_ram - base[1]; 378 #endif 379 380 fdt_fixup_memory_banks(blob, base, size, 2); 381 382 fsl_fdt_fixup_dr_usb(blob, bd); 383 384 fsl_fdt_fixup_flash(blob); 385 386 #ifdef CONFIG_FSL_MC_ENET 387 fdt_fixup_board_enet(blob); 388 #endif 389 390 return 0; 391 } 392 #endif 393 394 void qixis_dump_switch(void) 395 { 396 #ifdef CONFIG_FSL_QIXIS 397 int i, nr_of_cfgsw; 398 399 QIXIS_WRITE(cms[0], 0x00); 400 nr_of_cfgsw = QIXIS_READ(cms[1]); 401 402 puts("DIP switch settings dump:\n"); 403 for (i = 1; i <= nr_of_cfgsw; i++) { 404 QIXIS_WRITE(cms[0], i); 405 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); 406 } 407 #endif 408 } 409 410 /* 411 * Board rev C and earlier has duplicated I2C addresses for 2nd controller. 412 * Both slots has 0x54, resulting 2nd slot unusable. 413 */ 414 void update_spd_address(unsigned int ctrl_num, 415 unsigned int slot, 416 unsigned int *addr) 417 { 418 #ifndef CONFIG_TARGET_LS2081ARDB 419 #ifdef CONFIG_FSL_QIXIS 420 u8 sw; 421 422 sw = QIXIS_READ(arch); 423 if ((sw & 0xf) < 0x3) { 424 if (ctrl_num == 1 && slot == 0) 425 *addr = SPD_EEPROM_ADDRESS4; 426 else if (ctrl_num == 1 && slot == 1) 427 *addr = SPD_EEPROM_ADDRESS3; 428 } 429 #endif 430 #endif 431 } 432