1 /* 2 * Copyright 2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <malloc.h> 8 #include <errno.h> 9 #include <netdev.h> 10 #include <fsl_ifc.h> 11 #include <fsl_ddr.h> 12 #include <asm/io.h> 13 #include <hwconfig.h> 14 #include <fdt_support.h> 15 #include <libfdt.h> 16 #include <fsl-mc/fsl_mc.h> 17 #include <environment.h> 18 #include <efi_loader.h> 19 #include <i2c.h> 20 #include <asm/arch/mmu.h> 21 #include <asm/arch/soc.h> 22 #include <asm/arch/ppa.h> 23 #include <fsl_sec.h> 24 25 #include "../common/qixis.h" 26 #include "ls2080ardb_qixis.h" 27 #include "../common/vid.h" 28 29 #define PIN_MUX_SEL_SDHC 0x00 30 #define PIN_MUX_SEL_DSPI 0x0a 31 32 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value) 33 DECLARE_GLOBAL_DATA_PTR; 34 35 enum { 36 MUX_TYPE_SDHC, 37 MUX_TYPE_DSPI, 38 }; 39 40 unsigned long long get_qixis_addr(void) 41 { 42 unsigned long long addr; 43 44 if (gd->flags & GD_FLG_RELOC) 45 addr = QIXIS_BASE_PHYS; 46 else 47 addr = QIXIS_BASE_PHYS_EARLY; 48 49 /* 50 * IFC address under 256MB is mapped to 0x30000000, any address above 51 * is mapped to 0x5_10000000 up to 4GB. 52 */ 53 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; 54 55 return addr; 56 } 57 58 int checkboard(void) 59 { 60 u8 sw; 61 char buf[15]; 62 63 cpu_name(buf); 64 printf("Board: %s-RDB, ", buf); 65 66 sw = QIXIS_READ(arch); 67 printf("Board Arch: V%d, ", sw >> 4); 68 printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); 69 70 sw = QIXIS_READ(brdcfg[0]); 71 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 72 73 if (sw < 0x8) 74 printf("vBank: %d\n", sw); 75 else if (sw == 0x9) 76 puts("NAND\n"); 77 else 78 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 79 80 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); 81 82 puts("SERDES1 Reference : "); 83 printf("Clock1 = 156.25MHz "); 84 printf("Clock2 = 156.25MHz"); 85 86 puts("\nSERDES2 Reference : "); 87 printf("Clock1 = 100MHz "); 88 printf("Clock2 = 100MHz\n"); 89 90 return 0; 91 } 92 93 unsigned long get_board_sys_clk(void) 94 { 95 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 96 97 switch (sysclk_conf & 0x0F) { 98 case QIXIS_SYSCLK_83: 99 return 83333333; 100 case QIXIS_SYSCLK_100: 101 return 100000000; 102 case QIXIS_SYSCLK_125: 103 return 125000000; 104 case QIXIS_SYSCLK_133: 105 return 133333333; 106 case QIXIS_SYSCLK_150: 107 return 150000000; 108 case QIXIS_SYSCLK_160: 109 return 160000000; 110 case QIXIS_SYSCLK_166: 111 return 166666666; 112 } 113 return 66666666; 114 } 115 116 int select_i2c_ch_pca9547(u8 ch) 117 { 118 int ret; 119 120 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 121 if (ret) { 122 puts("PCA: failed to select proper channel\n"); 123 return ret; 124 } 125 126 return 0; 127 } 128 129 int i2c_multiplexer_select_vid_channel(u8 channel) 130 { 131 return select_i2c_ch_pca9547(channel); 132 } 133 134 int config_board_mux(int ctrl_type) 135 { 136 u8 reg5; 137 138 reg5 = QIXIS_READ(brdcfg[5]); 139 140 switch (ctrl_type) { 141 case MUX_TYPE_SDHC: 142 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC); 143 break; 144 case MUX_TYPE_DSPI: 145 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI); 146 break; 147 default: 148 printf("Wrong mux interface type\n"); 149 return -1; 150 } 151 152 QIXIS_WRITE(brdcfg[5], reg5); 153 154 return 0; 155 } 156 157 int board_init(void) 158 { 159 char *env_hwconfig; 160 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; 161 #ifdef CONFIG_FSL_MC_ENET 162 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; 163 #endif 164 u32 val; 165 166 init_final_memctl_regs(); 167 168 val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4); 169 170 env_hwconfig = getenv("hwconfig"); 171 172 if (hwconfig_f("dspi", env_hwconfig) && 173 DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8))) 174 config_board_mux(MUX_TYPE_DSPI); 175 else 176 config_board_mux(MUX_TYPE_SDHC); 177 178 #ifdef CONFIG_ENV_IS_NOWHERE 179 gd->env_addr = (ulong)&default_environment[0]; 180 #endif 181 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 182 183 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); 184 185 #ifdef CONFIG_FSL_LS_PPA 186 ppa_init(); 187 #endif 188 189 #ifdef CONFIG_FSL_MC_ENET 190 /* invert AQR405 IRQ pins polarity */ 191 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); 192 #endif 193 #ifdef CONFIG_FSL_CAAM 194 sec_init(); 195 #endif 196 197 return 0; 198 } 199 200 int board_early_init_f(void) 201 { 202 fsl_lsch3_early_init_f(); 203 return 0; 204 } 205 206 int misc_init_r(void) 207 { 208 if (hwconfig("sdhc")) 209 config_board_mux(MUX_TYPE_SDHC); 210 211 if (adjust_vdd(0)) 212 printf("Warning: Adjusting core voltage failed.\n"); 213 214 return 0; 215 } 216 217 void detail_board_ddr_info(void) 218 { 219 puts("\nDDR "); 220 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); 221 print_ddr_info(0); 222 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 223 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { 224 puts("\nDP-DDR "); 225 print_size(gd->bd->bi_dram[2].size, ""); 226 print_ddr_info(CONFIG_DP_DDR_CTRL); 227 } 228 #endif 229 } 230 231 #if defined(CONFIG_ARCH_MISC_INIT) 232 int arch_misc_init(void) 233 { 234 return 0; 235 } 236 #endif 237 238 #ifdef CONFIG_FSL_MC_ENET 239 void fdt_fixup_board_enet(void *fdt) 240 { 241 int offset; 242 243 offset = fdt_path_offset(fdt, "/soc/fsl-mc"); 244 245 if (offset < 0) 246 offset = fdt_path_offset(fdt, "/fsl-mc"); 247 248 if (offset < 0) { 249 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", 250 __func__, offset); 251 return; 252 } 253 254 if (get_mc_boot_status() == 0) 255 fdt_status_okay(fdt, offset); 256 else 257 fdt_status_fail(fdt, offset); 258 } 259 260 void board_quiesce_devices(void) 261 { 262 fsl_mc_ldpaa_exit(gd->bd); 263 } 264 #endif 265 266 #ifdef CONFIG_OF_BOARD_SETUP 267 int ft_board_setup(void *blob, bd_t *bd) 268 { 269 u64 base[CONFIG_NR_DRAM_BANKS]; 270 u64 size[CONFIG_NR_DRAM_BANKS]; 271 272 ft_cpu_setup(blob, bd); 273 274 /* fixup DT for the two GPP DDR banks */ 275 base[0] = gd->bd->bi_dram[0].start; 276 size[0] = gd->bd->bi_dram[0].size; 277 base[1] = gd->bd->bi_dram[1].start; 278 size[1] = gd->bd->bi_dram[1].size; 279 280 #ifdef CONFIG_RESV_RAM 281 /* reduce size if reserved memory is within this bank */ 282 if (gd->arch.resv_ram >= base[0] && 283 gd->arch.resv_ram < base[0] + size[0]) 284 size[0] = gd->arch.resv_ram - base[0]; 285 else if (gd->arch.resv_ram >= base[1] && 286 gd->arch.resv_ram < base[1] + size[1]) 287 size[1] = gd->arch.resv_ram - base[1]; 288 #endif 289 290 fdt_fixup_memory_banks(blob, base, size, 2); 291 292 fsl_fdt_fixup_dr_usb(blob, bd); 293 294 #ifdef CONFIG_FSL_MC_ENET 295 fdt_fixup_board_enet(blob); 296 #endif 297 298 return 0; 299 } 300 #endif 301 302 void qixis_dump_switch(void) 303 { 304 int i, nr_of_cfgsw; 305 306 QIXIS_WRITE(cms[0], 0x00); 307 nr_of_cfgsw = QIXIS_READ(cms[1]); 308 309 puts("DIP switch settings dump:\n"); 310 for (i = 1; i <= nr_of_cfgsw; i++) { 311 QIXIS_WRITE(cms[0], i); 312 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); 313 } 314 } 315 316 /* 317 * Board rev C and earlier has duplicated I2C addresses for 2nd controller. 318 * Both slots has 0x54, resulting 2nd slot unusable. 319 */ 320 void update_spd_address(unsigned int ctrl_num, 321 unsigned int slot, 322 unsigned int *addr) 323 { 324 u8 sw; 325 326 sw = QIXIS_READ(arch); 327 if ((sw & 0xf) < 0x3) { 328 if (ctrl_num == 1 && slot == 0) 329 *addr = SPD_EEPROM_ADDRESS4; 330 else if (ctrl_num == 1 && slot == 1) 331 *addr = SPD_EEPROM_ADDRESS3; 332 } 333 } 334