1 /*
2  * Copyright 2015 Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 #include <common.h>
7 #include <malloc.h>
8 #include <errno.h>
9 #include <netdev.h>
10 #include <fsl_ifc.h>
11 #include <fsl_ddr.h>
12 #include <asm/io.h>
13 #include <hwconfig.h>
14 #include <fdt_support.h>
15 #include <libfdt.h>
16 #include <fsl_debug_server.h>
17 #include <fsl-mc/fsl_mc.h>
18 #include <environment.h>
19 #include <i2c.h>
20 #include <asm/arch/soc.h>
21 
22 #include "../common/qixis.h"
23 #include "ls2080ardb_qixis.h"
24 
25 #define PIN_MUX_SEL_SDHC	0x00
26 #define PIN_MUX_SEL_DSPI	0x0a
27 
28 #define SET_SDHC_MUX_SEL(reg, value)	((reg & 0xf0) | value)
29 DECLARE_GLOBAL_DATA_PTR;
30 
31 enum {
32 	MUX_TYPE_SDHC,
33 	MUX_TYPE_DSPI,
34 };
35 
36 unsigned long long get_qixis_addr(void)
37 {
38 	unsigned long long addr;
39 
40 	if (gd->flags & GD_FLG_RELOC)
41 		addr = QIXIS_BASE_PHYS;
42 	else
43 		addr = QIXIS_BASE_PHYS_EARLY;
44 
45 	/*
46 	 * IFC address under 256MB is mapped to 0x30000000, any address above
47 	 * is mapped to 0x5_10000000 up to 4GB.
48 	 */
49 	addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
50 
51 	return addr;
52 }
53 
54 int checkboard(void)
55 {
56 	u8 sw;
57 	char buf[15];
58 
59 	cpu_name(buf);
60 	printf("Board: %s-RDB, ", buf);
61 
62 	sw = QIXIS_READ(arch);
63 	printf("Board Arch: V%d, ", sw >> 4);
64 	printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
65 
66 	sw = QIXIS_READ(brdcfg[0]);
67 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
68 
69 	if (sw < 0x8)
70 		printf("vBank: %d\n", sw);
71 	else if (sw == 0x9)
72 		puts("NAND\n");
73 	else
74 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
75 
76 	printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
77 
78 	puts("SERDES1 Reference : ");
79 	printf("Clock1 = 156.25MHz ");
80 	printf("Clock2 = 156.25MHz");
81 
82 	puts("\nSERDES2 Reference : ");
83 	printf("Clock1 = 100MHz ");
84 	printf("Clock2 = 100MHz\n");
85 
86 	return 0;
87 }
88 
89 unsigned long get_board_sys_clk(void)
90 {
91 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
92 
93 	switch (sysclk_conf & 0x0F) {
94 	case QIXIS_SYSCLK_83:
95 		return 83333333;
96 	case QIXIS_SYSCLK_100:
97 		return 100000000;
98 	case QIXIS_SYSCLK_125:
99 		return 125000000;
100 	case QIXIS_SYSCLK_133:
101 		return 133333333;
102 	case QIXIS_SYSCLK_150:
103 		return 150000000;
104 	case QIXIS_SYSCLK_160:
105 		return 160000000;
106 	case QIXIS_SYSCLK_166:
107 		return 166666666;
108 	}
109 	return 66666666;
110 }
111 
112 int select_i2c_ch_pca9547(u8 ch)
113 {
114 	int ret;
115 
116 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
117 	if (ret) {
118 		puts("PCA: failed to select proper channel\n");
119 		return ret;
120 	}
121 
122 	return 0;
123 }
124 
125 int config_board_mux(int ctrl_type)
126 {
127 	u8 reg5;
128 
129 	reg5 = QIXIS_READ(brdcfg[5]);
130 
131 	switch (ctrl_type) {
132 	case MUX_TYPE_SDHC:
133 		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
134 		break;
135 	case MUX_TYPE_DSPI:
136 		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
137 		break;
138 	default:
139 		printf("Wrong mux interface type\n");
140 		return -1;
141 	}
142 
143 	QIXIS_WRITE(brdcfg[5], reg5);
144 
145 	return 0;
146 }
147 
148 int board_init(void)
149 {
150 	char *env_hwconfig;
151 	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
152 	u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
153 	u32 val;
154 
155 	init_final_memctl_regs();
156 
157 	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
158 
159 	env_hwconfig = getenv("hwconfig");
160 
161 	if (hwconfig_f("dspi", env_hwconfig) &&
162 	    DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
163 		config_board_mux(MUX_TYPE_DSPI);
164 	else
165 		config_board_mux(MUX_TYPE_SDHC);
166 
167 #ifdef CONFIG_ENV_IS_NOWHERE
168 	gd->env_addr = (ulong)&default_environment[0];
169 #endif
170 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
171 
172 	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
173 
174 	/* invert AQR405 IRQ pins polarity */
175 	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
176 
177 	return 0;
178 }
179 
180 int board_early_init_f(void)
181 {
182 	fsl_lsch3_early_init_f();
183 	return 0;
184 }
185 
186 int misc_init_r(void)
187 {
188 	if (hwconfig("sdhc"))
189 		config_board_mux(MUX_TYPE_SDHC);
190 
191 	return 0;
192 }
193 
194 void detail_board_ddr_info(void)
195 {
196 	puts("\nDDR    ");
197 	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
198 	print_ddr_info(0);
199 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
200 	if (gd->bd->bi_dram[2].size) {
201 		puts("\nDP-DDR ");
202 		print_size(gd->bd->bi_dram[2].size, "");
203 		print_ddr_info(CONFIG_DP_DDR_CTRL);
204 	}
205 #endif
206 }
207 
208 int dram_init(void)
209 {
210 	gd->ram_size = initdram(0);
211 
212 	return 0;
213 }
214 
215 #if defined(CONFIG_ARCH_MISC_INIT)
216 int arch_misc_init(void)
217 {
218 #ifdef CONFIG_FSL_DEBUG_SERVER
219 	debug_server_init();
220 #endif
221 
222 	return 0;
223 }
224 #endif
225 
226 #ifdef CONFIG_FSL_MC_ENET
227 void fdt_fixup_board_enet(void *fdt)
228 {
229 	int offset;
230 
231 	offset = fdt_path_offset(fdt, "/fsl-mc");
232 
233 	if (offset < 0)
234 		offset = fdt_path_offset(fdt, "/fsl,dprc@0");
235 
236 	if (offset < 0) {
237 		printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
238 		       __func__, offset);
239 		return;
240 	}
241 
242 	if (get_mc_boot_status() == 0)
243 		fdt_status_okay(fdt, offset);
244 	else
245 		fdt_status_fail(fdt, offset);
246 }
247 #endif
248 
249 #ifdef CONFIG_OF_BOARD_SETUP
250 int ft_board_setup(void *blob, bd_t *bd)
251 {
252 	int err;
253 	u64 base[CONFIG_NR_DRAM_BANKS];
254 	u64 size[CONFIG_NR_DRAM_BANKS];
255 
256 	ft_cpu_setup(blob, bd);
257 
258 	/* fixup DT for the two GPP DDR banks */
259 	base[0] = gd->bd->bi_dram[0].start;
260 	size[0] = gd->bd->bi_dram[0].size;
261 	base[1] = gd->bd->bi_dram[1].start;
262 	size[1] = gd->bd->bi_dram[1].size;
263 
264 	fdt_fixup_memory_banks(blob, base, size, 2);
265 
266 #ifdef CONFIG_FSL_MC_ENET
267 	fdt_fixup_board_enet(blob);
268 	err = fsl_mc_ldpaa_exit(bd);
269 	if (err)
270 		return err;
271 #endif
272 
273 	return 0;
274 }
275 #endif
276 
277 void qixis_dump_switch(void)
278 {
279 	int i, nr_of_cfgsw;
280 
281 	QIXIS_WRITE(cms[0], 0x00);
282 	nr_of_cfgsw = QIXIS_READ(cms[1]);
283 
284 	puts("DIP switch settings dump:\n");
285 	for (i = 1; i <= nr_of_cfgsw; i++) {
286 		QIXIS_WRITE(cms[0], i);
287 		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
288 	}
289 }
290 
291 /*
292  * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
293  * Both slots has 0x54, resulting 2nd slot unusable.
294  */
295 void update_spd_address(unsigned int ctrl_num,
296 			unsigned int slot,
297 			unsigned int *addr)
298 {
299 	u8 sw;
300 
301 	sw = QIXIS_READ(arch);
302 	if ((sw & 0xf) < 0x3) {
303 		if (ctrl_num == 1 && slot == 0)
304 			*addr = SPD_EEPROM_ADDRESS4;
305 		else if (ctrl_num == 1 && slot == 1)
306 			*addr = SPD_EEPROM_ADDRESS3;
307 	}
308 }
309