1 /*
2  * Copyright 2015 Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 #include <common.h>
7 #include <malloc.h>
8 #include <errno.h>
9 #include <netdev.h>
10 #include <fsl_ifc.h>
11 #include <fsl_ddr.h>
12 #include <asm/io.h>
13 #include <hwconfig.h>
14 #include <fdt_support.h>
15 #include <libfdt.h>
16 #include <fsl-mc/fsl_mc.h>
17 #include <environment.h>
18 #include <i2c.h>
19 #include <asm/arch/soc.h>
20 #include <fsl_sec.h>
21 
22 #include "../common/qixis.h"
23 #include "ls2080ardb_qixis.h"
24 #include "../common/vid.h"
25 
26 #define PIN_MUX_SEL_SDHC	0x00
27 #define PIN_MUX_SEL_DSPI	0x0a
28 
29 #define SET_SDHC_MUX_SEL(reg, value)	((reg & 0xf0) | value)
30 DECLARE_GLOBAL_DATA_PTR;
31 
32 enum {
33 	MUX_TYPE_SDHC,
34 	MUX_TYPE_DSPI,
35 };
36 
37 unsigned long long get_qixis_addr(void)
38 {
39 	unsigned long long addr;
40 
41 	if (gd->flags & GD_FLG_RELOC)
42 		addr = QIXIS_BASE_PHYS;
43 	else
44 		addr = QIXIS_BASE_PHYS_EARLY;
45 
46 	/*
47 	 * IFC address under 256MB is mapped to 0x30000000, any address above
48 	 * is mapped to 0x5_10000000 up to 4GB.
49 	 */
50 	addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
51 
52 	return addr;
53 }
54 
55 int checkboard(void)
56 {
57 	u8 sw;
58 	char buf[15];
59 
60 	cpu_name(buf);
61 	printf("Board: %s-RDB, ", buf);
62 
63 	sw = QIXIS_READ(arch);
64 	printf("Board Arch: V%d, ", sw >> 4);
65 	printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
66 
67 	sw = QIXIS_READ(brdcfg[0]);
68 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
69 
70 	if (sw < 0x8)
71 		printf("vBank: %d\n", sw);
72 	else if (sw == 0x9)
73 		puts("NAND\n");
74 	else
75 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
76 
77 	printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
78 
79 	puts("SERDES1 Reference : ");
80 	printf("Clock1 = 156.25MHz ");
81 	printf("Clock2 = 156.25MHz");
82 
83 	puts("\nSERDES2 Reference : ");
84 	printf("Clock1 = 100MHz ");
85 	printf("Clock2 = 100MHz\n");
86 
87 	return 0;
88 }
89 
90 unsigned long get_board_sys_clk(void)
91 {
92 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
93 
94 	switch (sysclk_conf & 0x0F) {
95 	case QIXIS_SYSCLK_83:
96 		return 83333333;
97 	case QIXIS_SYSCLK_100:
98 		return 100000000;
99 	case QIXIS_SYSCLK_125:
100 		return 125000000;
101 	case QIXIS_SYSCLK_133:
102 		return 133333333;
103 	case QIXIS_SYSCLK_150:
104 		return 150000000;
105 	case QIXIS_SYSCLK_160:
106 		return 160000000;
107 	case QIXIS_SYSCLK_166:
108 		return 166666666;
109 	}
110 	return 66666666;
111 }
112 
113 int select_i2c_ch_pca9547(u8 ch)
114 {
115 	int ret;
116 
117 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
118 	if (ret) {
119 		puts("PCA: failed to select proper channel\n");
120 		return ret;
121 	}
122 
123 	return 0;
124 }
125 
126 int i2c_multiplexer_select_vid_channel(u8 channel)
127 {
128 	return select_i2c_ch_pca9547(channel);
129 }
130 
131 int config_board_mux(int ctrl_type)
132 {
133 	u8 reg5;
134 
135 	reg5 = QIXIS_READ(brdcfg[5]);
136 
137 	switch (ctrl_type) {
138 	case MUX_TYPE_SDHC:
139 		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
140 		break;
141 	case MUX_TYPE_DSPI:
142 		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
143 		break;
144 	default:
145 		printf("Wrong mux interface type\n");
146 		return -1;
147 	}
148 
149 	QIXIS_WRITE(brdcfg[5], reg5);
150 
151 	return 0;
152 }
153 
154 int board_init(void)
155 {
156 	char *env_hwconfig;
157 	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
158 #ifdef CONFIG_FSL_MC_ENET
159 	u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
160 #endif
161 	u32 val;
162 
163 	init_final_memctl_regs();
164 
165 	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
166 
167 	env_hwconfig = getenv("hwconfig");
168 
169 	if (hwconfig_f("dspi", env_hwconfig) &&
170 	    DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
171 		config_board_mux(MUX_TYPE_DSPI);
172 	else
173 		config_board_mux(MUX_TYPE_SDHC);
174 
175 #ifdef CONFIG_ENV_IS_NOWHERE
176 	gd->env_addr = (ulong)&default_environment[0];
177 #endif
178 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
179 
180 	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
181 
182 #ifdef CONFIG_FSL_MC_ENET
183 	/* invert AQR405 IRQ pins polarity */
184 	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
185 #endif
186 
187 	return 0;
188 }
189 
190 int board_early_init_f(void)
191 {
192 	fsl_lsch3_early_init_f();
193 	return 0;
194 }
195 
196 int misc_init_r(void)
197 {
198 	if (hwconfig("sdhc"))
199 		config_board_mux(MUX_TYPE_SDHC);
200 
201 	if (adjust_vdd(0))
202 		printf("Warning: Adjusting core voltage failed.\n");
203 
204 	return 0;
205 }
206 
207 void detail_board_ddr_info(void)
208 {
209 	puts("\nDDR    ");
210 	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
211 	print_ddr_info(0);
212 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
213 	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
214 		puts("\nDP-DDR ");
215 		print_size(gd->bd->bi_dram[2].size, "");
216 		print_ddr_info(CONFIG_DP_DDR_CTRL);
217 	}
218 #endif
219 }
220 
221 int dram_init(void)
222 {
223 	gd->ram_size = initdram(0);
224 
225 	return 0;
226 }
227 
228 #if defined(CONFIG_ARCH_MISC_INIT)
229 int arch_misc_init(void)
230 {
231 #ifdef CONFIG_FSL_CAAM
232 	sec_init();
233 #endif
234 	return 0;
235 }
236 #endif
237 
238 #ifdef CONFIG_FSL_MC_ENET
239 void fdt_fixup_board_enet(void *fdt)
240 {
241 	int offset;
242 
243 	offset = fdt_path_offset(fdt, "/soc/fsl-mc");
244 
245 	if (offset < 0)
246 		offset = fdt_path_offset(fdt, "/fsl-mc");
247 
248 	if (offset < 0) {
249 		printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
250 		       __func__, offset);
251 		return;
252 	}
253 
254 	if (get_mc_boot_status() == 0)
255 		fdt_status_okay(fdt, offset);
256 	else
257 		fdt_status_fail(fdt, offset);
258 }
259 #endif
260 
261 #ifdef CONFIG_OF_BOARD_SETUP
262 int ft_board_setup(void *blob, bd_t *bd)
263 {
264 #ifdef CONFIG_FSL_MC_ENET
265 	int err;
266 #endif
267 	u64 base[CONFIG_NR_DRAM_BANKS];
268 	u64 size[CONFIG_NR_DRAM_BANKS];
269 
270 	ft_cpu_setup(blob, bd);
271 
272 	/* fixup DT for the two GPP DDR banks */
273 	base[0] = gd->bd->bi_dram[0].start;
274 	size[0] = gd->bd->bi_dram[0].size;
275 	base[1] = gd->bd->bi_dram[1].start;
276 	size[1] = gd->bd->bi_dram[1].size;
277 
278 	fdt_fixup_memory_banks(blob, base, size, 2);
279 
280 	fdt_fixup_dr_usb(blob, bd);
281 
282 #ifdef CONFIG_FSL_MC_ENET
283 	fdt_fixup_board_enet(blob);
284 	err = fsl_mc_ldpaa_exit(bd);
285 	if (err)
286 		return err;
287 #endif
288 
289 	return 0;
290 }
291 #endif
292 
293 void qixis_dump_switch(void)
294 {
295 	int i, nr_of_cfgsw;
296 
297 	QIXIS_WRITE(cms[0], 0x00);
298 	nr_of_cfgsw = QIXIS_READ(cms[1]);
299 
300 	puts("DIP switch settings dump:\n");
301 	for (i = 1; i <= nr_of_cfgsw; i++) {
302 		QIXIS_WRITE(cms[0], i);
303 		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
304 	}
305 }
306 
307 /*
308  * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
309  * Both slots has 0x54, resulting 2nd slot unusable.
310  */
311 void update_spd_address(unsigned int ctrl_num,
312 			unsigned int slot,
313 			unsigned int *addr)
314 {
315 	u8 sw;
316 
317 	sw = QIXIS_READ(arch);
318 	if ((sw & 0xf) < 0x3) {
319 		if (ctrl_num == 1 && slot == 0)
320 			*addr = SPD_EEPROM_ADDRESS4;
321 		else if (ctrl_num == 1 && slot == 1)
322 			*addr = SPD_EEPROM_ADDRESS3;
323 	}
324 }
325