1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2015 Freescale Semiconductor, Inc.
4  *
5  */
6 
7 #include <common.h>
8 #include <command.h>
9 #include <netdev.h>
10 #include <malloc.h>
11 #include <fsl_mdio.h>
12 #include <miiphy.h>
13 #include <phy.h>
14 #include <fm_eth.h>
15 #include <asm/io.h>
16 #include <exports.h>
17 #include <asm/arch/fsl_serdes.h>
18 #include <fsl-mc/fsl_mc.h>
19 #include <fsl-mc/ldpaa_wriop.h>
20 
21 DECLARE_GLOBAL_DATA_PTR;
22 
23 int board_eth_init(bd_t *bis)
24 {
25 #if defined(CONFIG_FSL_MC_ENET)
26 	int i, interface;
27 	struct memac_mdio_info mdio_info;
28 	struct mii_dev *dev;
29 	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
30 	u32 srds_s1;
31 	struct memac_mdio_controller *reg;
32 
33 	srds_s1 = in_le32(&gur->rcwsr[28]) &
34 				FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
35 	srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
36 
37 	reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
38 	mdio_info.regs = reg;
39 	mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
40 
41 	/* Register the EMI 1 */
42 	fm_memac_mdio_init(bis, &mdio_info);
43 
44 	reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
45 	mdio_info.regs = reg;
46 	mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
47 
48 	/* Register the EMI 2 */
49 	fm_memac_mdio_init(bis, &mdio_info);
50 
51 	switch (srds_s1) {
52 	case 0x2A:
53 		wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
54 		wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
55 		wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
56 		wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
57 		wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
58 		wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
59 		wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
60 		wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
61 
62 		break;
63 	case 0x4B:
64 		wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
65 		wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
66 		wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
67 		wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
68 
69 		break;
70 	default:
71 		printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n",
72 		       srds_s1);
73 		break;
74 	}
75 
76 	for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) {
77 		interface = wriop_get_enet_if(i);
78 		switch (interface) {
79 		case PHY_INTERFACE_MODE_XGMII:
80 			dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
81 			wriop_set_mdio(i, dev);
82 			break;
83 		default:
84 			break;
85 		}
86 	}
87 
88 	for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) {
89 		switch (wriop_get_enet_if(i)) {
90 		case PHY_INTERFACE_MODE_XGMII:
91 			dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
92 			wriop_set_mdio(i, dev);
93 			break;
94 		default:
95 			break;
96 		}
97 	}
98 
99 	cpu_eth_init(bis);
100 #endif /* CONFIG_FSL_MC_ENET */
101 
102 #ifdef CONFIG_PHY_AQUANTIA
103 	/*
104 	 * Export functions to be used by AQ firmware
105 	 * upload application
106 	 */
107 	gd->jt->strcpy = strcpy;
108 	gd->jt->mdelay = mdelay;
109 	gd->jt->mdio_get_current_dev = mdio_get_current_dev;
110 	gd->jt->phy_find_by_mask = phy_find_by_mask;
111 	gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
112 	gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
113 #endif
114 	return pci_eth_init(bis);
115 }
116 
117 #if defined(CONFIG_RESET_PHY_R)
118 void reset_phy(void)
119 {
120 	mc_env_boot();
121 }
122 #endif /* CONFIG_RESET_PHY_R */
123