1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __DDR_H__ 8 #define __DDR_H__ 9 struct board_specific_parameters { 10 u32 n_ranks; 11 u32 datarate_mhz_high; 12 u32 rank_gb; 13 u32 clk_adjust; 14 u32 wrlvl_start; 15 u32 wrlvl_ctl_2; 16 u32 wrlvl_ctl_3; 17 }; 18 19 /* 20 * These tables contain all valid speeds we want to override with board 21 * specific parameters. datarate_mhz_high values need to be in ascending order 22 * for each n_ranks group. 23 */ 24 25 static const struct board_specific_parameters udimm0[] = { 26 /* 27 * memory controller 0 28 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 29 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 30 */ 31 {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, 32 {2, 1666, 0, 10, 9, 0x090A0B0E, 0x0F11110C,}, 33 {2, 1900, 0, 12, 0xA, 0x0B0C0E11, 0x1214140F,}, 34 {2, 2300, 0, 12, 0xB, 0x0C0D0F12, 0x14161610,}, 35 {} 36 }; 37 38 /* DP-DDR DIMM */ 39 static const struct board_specific_parameters udimm2[] = { 40 /* 41 * memory controller 2 42 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 43 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 44 */ 45 {2, 1350, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,}, 46 {2, 1666, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,}, 47 {2, 1900, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,}, 48 {2, 2200, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,}, 49 {} 50 }; 51 52 static const struct board_specific_parameters rdimm0[] = { 53 /* 54 * memory controller 0 55 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 56 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 57 */ 58 {2, 1666, 0, 8, 0x0F, 0x0D0C0A09, 0x0B0C0E08,}, 59 {2, 1900, 0, 8, 0x10, 0x0F0D0B0A, 0x0B0E0F09,}, 60 {2, 2200, 0, 8, 0x13, 0x120F0E0B, 0x0D10110B,}, 61 {} 62 }; 63 64 static const struct board_specific_parameters *udimms[] = { 65 udimm0, 66 udimm0, 67 udimm2, 68 }; 69 70 static const struct board_specific_parameters *rdimms[] = { 71 rdimm0, 72 rdimm0, 73 udimm2, /* DP-DDR doesn't support RDIMM */ 74 }; 75 76 77 #endif 78