1Overview
2--------
3The LS2080A Reference Design (RDB) is a high-performance computing,
4evaluation, and development platform that supports the QorIQ LS2080A
5Layerscape Architecture processor.
6
7LS2080A SoC Overview
8------------------
9The LS2080A integrated multicore processor combines eight ARM Cortex-A57
10processor cores with high-performance data path acceleration logic and network
11and peripheral bus interfaces required for networking, telecom/datacom,
12wireless infrastructure, and mil/aerospace applications.
13
14The LS2080A SoC includes the following function and features:
15
16 - Eight 64-bit ARM Cortex-A57 CPUs
17 - 1 MB platform cache with ECC
18 - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
19 - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
20  the AIOP
21 - Data path acceleration architecture (DPAA2) incorporating acceleration for
22 the following functions:
23   - Packet parsing, classification, and distribution (WRIOP)
24   - Queue and Hardware buffer management for scheduling, packet sequencing, and
25     congestion management, buffer allocation and de-allocation (QBMan)
26   - Cryptography acceleration (SEC) at up to 10 Gbps
27   - RegEx pattern matching acceleration (PME) at up to 10 Gbps
28   - Decompression/compression acceleration (DCE) at up to 20 Gbps
29   - Accelerated I/O processing (AIOP) at up to 20 Gbps
30   - QDMA engine
31 - 16 SerDes lanes at up to 10.3125 GHz
32 - Ethernet interfaces
33   - Up to eight 10 Gbps Ethernet MACs
34   - Up to eight 1 / 2.5 Gbps Ethernet MACs
35 - High-speed peripheral interfaces
36   - Four PCIe 3.0 controllers, one supporting SR-IOV
37 - Additional peripheral interfaces
38   - Two serial ATA (SATA 3.0) controllers
39   - Two high-speed USB 3.0 controllers with integrated PHY
40   - Enhanced secure digital host controller (eSDXC/eMMC)
41   - Serial peripheral interface (SPI) controller
42   - Quad Serial Peripheral Interface (QSPI) Controller
43   - Four I2C controllers
44   - Two DUARTs
45   - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
46 - Support for hardware virtualization and partitioning enforcement
47 - QorIQ platform's trust architecture 3.0
48 - Service processor (SP) provides pre-boot initialization and secure-boot
49  capabilities
50
51 LS2080ARDB board Overview
52 -----------------------
53 - SERDES Connections, 16 lanes supporting:
54      - PCI Express - 3.0
55      - SATA 3.0
56      - XFI
57 - DDR Controller
58     - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
59       chip-selects and two DIMM connectors. Support is up to 2133MT/s.
60     - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects
61       and two DIMM connectors. Support is up to 1600MT/s.
62 -IFC/Local Bus
63    - IFC rev. 2.0 implementation supporting Little Endian connection scheme.
64    - 128 MB NOR flash 16-bit data bus
65    - One 2 GB NAND flash with ECC support
66    - CPLD connection
67 - USB 3.0
68    - Two high speed USB 3.0 ports
69    - First USB 3.0 port configured as Host with Type-A connector
70    - Second USB 3.0 port configured as OTG with micro-AB connector
71 - SDHC adapter
72    - SD Card Rev 2.0 and Rev 3.0
73 - DSPI
74    - 128 MB high-speed flash Memory for boot code and storage (up to 108MHz)
75 - 4 I2C controllers
76 - Two SATA onboard connectors
77 - UART
78 - ARM JTAG support
79
80Memory map from core's view
81----------------------------
820x00_0000_0000 .. 0x00_000F_FFFF	Boot Rom
830x00_0100_0000 .. 0x00_0FFF_FFFF	CCSR
840x00_1800_0000 .. 0x00_181F_FFFF	OCRAM
850x00_3000_0000 .. 0x00_3FFF_FFFF	IFC region #1
860x00_8000_0000 .. 0x00_FFFF_FFFF	DDR region #1
870x05_1000_0000 .. 0x05_FFFF_FFFF	IFC region #2
880x80_8000_0000 .. 0xFF_FFFF_FFFF	DDR region #2
89
90Other addresses are either reserved, or not used directly by u-boot.
91This list should be updated when more addresses are used.
92
93IFC region map from core's view
94-------------------------------
95During boot i.e. IFC Region #1:-
96  0x30000000 - 0x37ffffff : 128MB : NOR flash
97  0x3C000000 - 0x40000000 : 64MB  : CPLD
98
99After relocate to DDR i.e. IFC Region #2:-
100  0x5_1000_0000..0x5_1fff_ffff	Memory Hole
101  0x5_2000_0000..0x5_3fff_ffff	IFC CSx (CPLD, NAND and others 512MB)
102  0x5_4000_0000..0x5_7fff_ffff	ASIC or others 1GB
103  0x5_8000_0000..0x5_bfff_ffff	IFC CS0 1GB (NOR/Promjet)
104  0x5_C000_0000..0x5_ffff_ffff	IFC CS1 1GB (NOR/Promjet)
105
106Booting Options
107---------------
108a) NOR boot
109b) NAND boot
110
111Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
112-------------------------------------------------------------------
113One needs to use appropriate bootargs to boot Linux flavors which do
114not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
115below:
116
117=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram
118   earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
119   hugepages=16 mem=2048M'
120
121