1Overview
2--------
3The LS2080A Reference Design (RDB) is a high-performance computing,
4evaluation, and development platform that supports the QorIQ LS2080A
5Layerscape Architecture processor.
6
7LS2080A SoC Overview
8--------------------
9Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
10SoC overview.
11
12 LS2080ARDB board Overview
13 -----------------------
14 - SERDES Connections, 16 lanes supporting:
15      - PCI Express - 3.0
16      - SATA 3.0
17      - XFI
18 - DDR Controller
19     - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
20       chip-selects and two DIMM connectors. Support is up to 2133MT/s.
21     - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects
22       and two DIMM connectors. Support is up to 1600MT/s.
23 -IFC/Local Bus
24    - IFC rev. 2.0 implementation supporting Little Endian connection scheme.
25    - 128 MB NOR flash 16-bit data bus
26    - One 2 GB NAND flash with ECC support
27    - CPLD connection
28 - USB 3.0
29    - Two high speed USB 3.0 ports
30    - First USB 3.0 port configured as Host with Type-A connector
31    - Second USB 3.0 port configured as OTG with micro-AB connector
32 - SDHC adapter
33    - SD Card Rev 2.0 and Rev 3.0
34 - DSPI
35    - 128 MB high-speed flash Memory for boot code and storage (up to 108MHz)
36 - 4 I2C controllers
37 - Two SATA onboard connectors
38 - UART
39 - ARM JTAG support
40
41Memory map from core's view
42----------------------------
430x00_0000_0000 .. 0x00_000F_FFFF	Boot Rom
440x00_0100_0000 .. 0x00_0FFF_FFFF	CCSR
450x00_1800_0000 .. 0x00_181F_FFFF	OCRAM
460x00_3000_0000 .. 0x00_3FFF_FFFF	IFC region #1
470x00_8000_0000 .. 0x00_FFFF_FFFF	DDR region #1
480x05_1000_0000 .. 0x05_FFFF_FFFF	IFC region #2
490x80_8000_0000 .. 0xFF_FFFF_FFFF	DDR region #2
50
51Other addresses are either reserved, or not used directly by U-Boot.
52This list should be updated when more addresses are used.
53
54IFC region map from core's view
55-------------------------------
56During boot i.e. IFC Region #1:-
57  0x30000000 - 0x37ffffff : 128MB : NOR flash
58  0x3C000000 - 0x40000000 : 64MB  : CPLD
59
60After relocate to DDR i.e. IFC Region #2:-
61  0x5_1000_0000..0x5_1fff_ffff	Memory Hole
62  0x5_2000_0000..0x5_3fff_ffff	IFC CSx (CPLD, NAND and others 512MB)
63  0x5_4000_0000..0x5_7fff_ffff	ASIC or others 1GB
64  0x5_8000_0000..0x5_bfff_ffff	IFC CS0 1GB (NOR/Promjet)
65  0x5_C000_0000..0x5_ffff_ffff	IFC CS1 1GB (NOR/Promjet)
66
67Booting Options
68---------------
69a) NOR boot
70b) NAND boot
71
72Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
73-------------------------------------------------------------------
74One needs to use appropriate bootargs to boot Linux flavors which do
75not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
76below:
77
78=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram
79   earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
80   hugepages=16 mem=2048M'
81
82