1 /*
2  * Copyright 2015 Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 #include <common.h>
7 #include <malloc.h>
8 #include <errno.h>
9 #include <netdev.h>
10 #include <fsl_ifc.h>
11 #include <fsl_ddr.h>
12 #include <asm/io.h>
13 #include <fdt_support.h>
14 #include <libfdt.h>
15 #include <fsl-mc/fsl_mc.h>
16 #include <environment.h>
17 #include <i2c.h>
18 #include <rtc.h>
19 #include <asm/arch/soc.h>
20 #include <hwconfig.h>
21 #include <fsl_sec.h>
22 
23 #include "../common/qixis.h"
24 #include "ls2080aqds_qixis.h"
25 
26 #define PIN_MUX_SEL_SDHC	0x00
27 #define PIN_MUX_SEL_DSPI	0x0a
28 #define SCFG_QSPICLKCTRL_DIV_20	(5 << 27)
29 
30 #define SET_SDHC_MUX_SEL(reg, value)	((reg & 0xf0) | value)
31 
32 DECLARE_GLOBAL_DATA_PTR;
33 
34 enum {
35 	MUX_TYPE_SDHC,
36 	MUX_TYPE_DSPI,
37 };
38 
39 unsigned long long get_qixis_addr(void)
40 {
41 	unsigned long long addr;
42 
43 	if (gd->flags & GD_FLG_RELOC)
44 		addr = QIXIS_BASE_PHYS;
45 	else
46 		addr = QIXIS_BASE_PHYS_EARLY;
47 
48 	/*
49 	 * IFC address under 256MB is mapped to 0x30000000, any address above
50 	 * is mapped to 0x5_10000000 up to 4GB.
51 	 */
52 	addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
53 
54 	return addr;
55 }
56 
57 int checkboard(void)
58 {
59 	char buf[64];
60 	u8 sw;
61 	static const char *const freq[] = {"100", "125", "156.25",
62 					    "100 separate SSCG"};
63 	int clock;
64 
65 	cpu_name(buf);
66 	printf("Board: %s-QDS, ", buf);
67 
68 	sw = QIXIS_READ(arch);
69 	printf("Board Arch: V%d, ", sw >> 4);
70 	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
71 
72 	memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
73 
74 	sw = QIXIS_READ(brdcfg[0]);
75 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
76 
77 	if (sw < 0x8)
78 		printf("vBank: %d\n", sw);
79 	else if (sw == 0x8)
80 		puts("PromJet\n");
81 	else if (sw == 0x9)
82 		puts("NAND\n");
83 	else if (sw == 0xf)
84 		puts("QSPI\n");
85 	else if (sw == 0x15)
86 		printf("IFCCard\n");
87 	else
88 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
89 
90 	printf("FPGA: v%d (%s), build %d",
91 	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
92 	       (int)qixis_read_minor());
93 	/* the timestamp string contains "\n" at the end */
94 	printf(" on %s", qixis_read_time(buf));
95 
96 	/*
97 	 * Display the actual SERDES reference clocks as configured by the
98 	 * dip switches on the board.  Note that the SWx registers could
99 	 * technically be set to force the reference clocks to match the
100 	 * values that the SERDES expects (or vice versa).  For now, however,
101 	 * we just display both values and hope the user notices when they
102 	 * don't match.
103 	 */
104 	puts("SERDES1 Reference : ");
105 	sw = QIXIS_READ(brdcfg[2]);
106 	clock = (sw >> 6) & 3;
107 	printf("Clock1 = %sMHz ", freq[clock]);
108 	clock = (sw >> 4) & 3;
109 	printf("Clock2 = %sMHz", freq[clock]);
110 
111 	puts("\nSERDES2 Reference : ");
112 	clock = (sw >> 2) & 3;
113 	printf("Clock1 = %sMHz ", freq[clock]);
114 	clock = (sw >> 0) & 3;
115 	printf("Clock2 = %sMHz\n", freq[clock]);
116 
117 	return 0;
118 }
119 
120 unsigned long get_board_sys_clk(void)
121 {
122 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
123 
124 	switch (sysclk_conf & 0x0F) {
125 	case QIXIS_SYSCLK_83:
126 		return 83333333;
127 	case QIXIS_SYSCLK_100:
128 		return 100000000;
129 	case QIXIS_SYSCLK_125:
130 		return 125000000;
131 	case QIXIS_SYSCLK_133:
132 		return 133333333;
133 	case QIXIS_SYSCLK_150:
134 		return 150000000;
135 	case QIXIS_SYSCLK_160:
136 		return 160000000;
137 	case QIXIS_SYSCLK_166:
138 		return 166666666;
139 	}
140 	return 66666666;
141 }
142 
143 unsigned long get_board_ddr_clk(void)
144 {
145 	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
146 
147 	switch ((ddrclk_conf & 0x30) >> 4) {
148 	case QIXIS_DDRCLK_100:
149 		return 100000000;
150 	case QIXIS_DDRCLK_125:
151 		return 125000000;
152 	case QIXIS_DDRCLK_133:
153 		return 133333333;
154 	}
155 	return 66666666;
156 }
157 
158 int select_i2c_ch_pca9547(u8 ch)
159 {
160 	int ret;
161 
162 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
163 	if (ret) {
164 		puts("PCA: failed to select proper channel\n");
165 		return ret;
166 	}
167 
168 	return 0;
169 }
170 
171 int config_board_mux(int ctrl_type)
172 {
173 	u8 reg5;
174 
175 	reg5 = QIXIS_READ(brdcfg[5]);
176 
177 	switch (ctrl_type) {
178 	case MUX_TYPE_SDHC:
179 		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
180 		break;
181 	case MUX_TYPE_DSPI:
182 		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
183 		break;
184 	default:
185 		printf("Wrong mux interface type\n");
186 		return -1;
187 	}
188 
189 	QIXIS_WRITE(brdcfg[5], reg5);
190 
191 	return 0;
192 }
193 
194 int board_init(void)
195 {
196 	char *env_hwconfig;
197 	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
198 	u32 val;
199 
200 	init_final_memctl_regs();
201 
202 	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
203 
204 	env_hwconfig = getenv("hwconfig");
205 
206 	if (hwconfig_f("dspi", env_hwconfig) &&
207 	    DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
208 		config_board_mux(MUX_TYPE_DSPI);
209 	else
210 		config_board_mux(MUX_TYPE_SDHC);
211 
212 #if defined(CONFIG_NAND) && defined(CONFIG_FSL_QSPI)
213 	val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
214 
215 	if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
216 		QIXIS_WRITE(brdcfg[9],
217 			    (QIXIS_READ(brdcfg[9]) & 0xf8) |
218 			     FSL_QIXIS_BRDCFG9_QSPI);
219 #endif
220 
221 #ifdef CONFIG_ENV_IS_NOWHERE
222 	gd->env_addr = (ulong)&default_environment[0];
223 #endif
224 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
225 	rtc_enable_32khz_output();
226 
227 	return 0;
228 }
229 
230 int board_early_init_f(void)
231 {
232 #ifdef CONFIG_SYS_I2C_EARLY_INIT
233 	i2c_early_init_f();
234 #endif
235 	fsl_lsch3_early_init_f();
236 #ifdef CONFIG_FSL_QSPI
237 	/* input clk: 1/2 platform clk, output: input/20 */
238 	out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
239 #endif
240 	return 0;
241 }
242 
243 void detail_board_ddr_info(void)
244 {
245 	puts("\nDDR    ");
246 	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
247 	print_ddr_info(0);
248 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
249 	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
250 		puts("\nDP-DDR ");
251 		print_size(gd->bd->bi_dram[2].size, "");
252 		print_ddr_info(CONFIG_DP_DDR_CTRL);
253 	}
254 #endif
255 }
256 
257 int dram_init(void)
258 {
259 	gd->ram_size = initdram(0);
260 
261 	return 0;
262 }
263 
264 #if defined(CONFIG_ARCH_MISC_INIT)
265 int arch_misc_init(void)
266 {
267 #ifdef CONFIG_FSL_CAAM
268 	sec_init();
269 #endif
270 	return 0;
271 }
272 #endif
273 
274 #ifdef CONFIG_FSL_MC_ENET
275 void fdt_fixup_board_enet(void *fdt)
276 {
277 	int offset;
278 
279 	offset = fdt_path_offset(fdt, "/soc/fsl-mc");
280 
281 	if (offset < 0)
282 		offset = fdt_path_offset(fdt, "/fsl-mc");
283 
284 	if (offset < 0) {
285 		printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
286 		       __func__, offset);
287 		return;
288 	}
289 
290 	if (get_mc_boot_status() == 0)
291 		fdt_status_okay(fdt, offset);
292 	else
293 		fdt_status_fail(fdt, offset);
294 }
295 #endif
296 
297 #ifdef CONFIG_OF_BOARD_SETUP
298 int ft_board_setup(void *blob, bd_t *bd)
299 {
300 #ifdef CONFIG_FSL_MC_ENET
301 	int err;
302 #endif
303 	u64 base[CONFIG_NR_DRAM_BANKS];
304 	u64 size[CONFIG_NR_DRAM_BANKS];
305 
306 	ft_cpu_setup(blob, bd);
307 
308 	/* fixup DT for the two GPP DDR banks */
309 	base[0] = gd->bd->bi_dram[0].start;
310 	size[0] = gd->bd->bi_dram[0].size;
311 	base[1] = gd->bd->bi_dram[1].start;
312 	size[1] = gd->bd->bi_dram[1].size;
313 
314 	fdt_fixup_memory_banks(blob, base, size, 2);
315 
316 	fsl_fdt_fixup_dr_usb(blob, bd);
317 
318 #ifdef CONFIG_FSL_MC_ENET
319 	fdt_fixup_board_enet(blob);
320 	err = fsl_mc_ldpaa_exit(bd);
321 	if (err)
322 		return err;
323 #endif
324 
325 	return 0;
326 }
327 #endif
328 
329 void qixis_dump_switch(void)
330 {
331 	int i, nr_of_cfgsw;
332 
333 	QIXIS_WRITE(cms[0], 0x00);
334 	nr_of_cfgsw = QIXIS_READ(cms[1]);
335 
336 	puts("DIP switch settings dump:\n");
337 	for (i = 1; i <= nr_of_cfgsw; i++) {
338 		QIXIS_WRITE(cms[0], i);
339 		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
340 	}
341 }
342