1 /*
2  * Copyright 2015 Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 #include <common.h>
7 #include <malloc.h>
8 #include <errno.h>
9 #include <netdev.h>
10 #include <fsl_ifc.h>
11 #include <fsl_ddr.h>
12 #include <asm/io.h>
13 #include <fdt_support.h>
14 #include <libfdt.h>
15 #include <fsl_debug_server.h>
16 #include <fsl-mc/fsl_mc.h>
17 #include <environment.h>
18 #include <i2c.h>
19 #include <rtc.h>
20 #include <asm/arch/soc.h>
21 #include <hwconfig.h>
22 #include <fsl_sec.h>
23 
24 #include "../common/qixis.h"
25 #include "ls2080aqds_qixis.h"
26 
27 #define PIN_MUX_SEL_SDHC	0x00
28 #define PIN_MUX_SEL_DSPI	0x0a
29 #define SCFG_QSPICLKCTRL_DIV_20	(5 << 27)
30 
31 #define SET_SDHC_MUX_SEL(reg, value)	((reg & 0xf0) | value)
32 
33 DECLARE_GLOBAL_DATA_PTR;
34 
35 enum {
36 	MUX_TYPE_SDHC,
37 	MUX_TYPE_DSPI,
38 };
39 
40 unsigned long long get_qixis_addr(void)
41 {
42 	unsigned long long addr;
43 
44 	if (gd->flags & GD_FLG_RELOC)
45 		addr = QIXIS_BASE_PHYS;
46 	else
47 		addr = QIXIS_BASE_PHYS_EARLY;
48 
49 	/*
50 	 * IFC address under 256MB is mapped to 0x30000000, any address above
51 	 * is mapped to 0x5_10000000 up to 4GB.
52 	 */
53 	addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
54 
55 	return addr;
56 }
57 
58 int checkboard(void)
59 {
60 	char buf[64];
61 	u8 sw;
62 	static const char *const freq[] = {"100", "125", "156.25",
63 					    "100 separate SSCG"};
64 	int clock;
65 
66 	cpu_name(buf);
67 	printf("Board: %s-QDS, ", buf);
68 
69 	sw = QIXIS_READ(arch);
70 	printf("Board Arch: V%d, ", sw >> 4);
71 	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
72 
73 	memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
74 
75 	sw = QIXIS_READ(brdcfg[0]);
76 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
77 
78 	if (sw < 0x8)
79 		printf("vBank: %d\n", sw);
80 	else if (sw == 0x8)
81 		puts("PromJet\n");
82 	else if (sw == 0x9)
83 		puts("NAND\n");
84 	else if (sw == 0xf)
85 		puts("QSPI\n");
86 	else if (sw == 0x15)
87 		printf("IFCCard\n");
88 	else
89 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
90 
91 	printf("FPGA: v%d (%s), build %d",
92 	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
93 	       (int)qixis_read_minor());
94 	/* the timestamp string contains "\n" at the end */
95 	printf(" on %s", qixis_read_time(buf));
96 
97 	/*
98 	 * Display the actual SERDES reference clocks as configured by the
99 	 * dip switches on the board.  Note that the SWx registers could
100 	 * technically be set to force the reference clocks to match the
101 	 * values that the SERDES expects (or vice versa).  For now, however,
102 	 * we just display both values and hope the user notices when they
103 	 * don't match.
104 	 */
105 	puts("SERDES1 Reference : ");
106 	sw = QIXIS_READ(brdcfg[2]);
107 	clock = (sw >> 6) & 3;
108 	printf("Clock1 = %sMHz ", freq[clock]);
109 	clock = (sw >> 4) & 3;
110 	printf("Clock2 = %sMHz", freq[clock]);
111 
112 	puts("\nSERDES2 Reference : ");
113 	clock = (sw >> 2) & 3;
114 	printf("Clock1 = %sMHz ", freq[clock]);
115 	clock = (sw >> 0) & 3;
116 	printf("Clock2 = %sMHz\n", freq[clock]);
117 
118 	return 0;
119 }
120 
121 unsigned long get_board_sys_clk(void)
122 {
123 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
124 
125 	switch (sysclk_conf & 0x0F) {
126 	case QIXIS_SYSCLK_83:
127 		return 83333333;
128 	case QIXIS_SYSCLK_100:
129 		return 100000000;
130 	case QIXIS_SYSCLK_125:
131 		return 125000000;
132 	case QIXIS_SYSCLK_133:
133 		return 133333333;
134 	case QIXIS_SYSCLK_150:
135 		return 150000000;
136 	case QIXIS_SYSCLK_160:
137 		return 160000000;
138 	case QIXIS_SYSCLK_166:
139 		return 166666666;
140 	}
141 	return 66666666;
142 }
143 
144 unsigned long get_board_ddr_clk(void)
145 {
146 	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
147 
148 	switch ((ddrclk_conf & 0x30) >> 4) {
149 	case QIXIS_DDRCLK_100:
150 		return 100000000;
151 	case QIXIS_DDRCLK_125:
152 		return 125000000;
153 	case QIXIS_DDRCLK_133:
154 		return 133333333;
155 	}
156 	return 66666666;
157 }
158 
159 int select_i2c_ch_pca9547(u8 ch)
160 {
161 	int ret;
162 
163 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
164 	if (ret) {
165 		puts("PCA: failed to select proper channel\n");
166 		return ret;
167 	}
168 
169 	return 0;
170 }
171 
172 int config_board_mux(int ctrl_type)
173 {
174 	u8 reg5;
175 
176 	reg5 = QIXIS_READ(brdcfg[5]);
177 
178 	switch (ctrl_type) {
179 	case MUX_TYPE_SDHC:
180 		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
181 		break;
182 	case MUX_TYPE_DSPI:
183 		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
184 		break;
185 	default:
186 		printf("Wrong mux interface type\n");
187 		return -1;
188 	}
189 
190 	QIXIS_WRITE(brdcfg[5], reg5);
191 
192 	return 0;
193 }
194 
195 int board_init(void)
196 {
197 	char *env_hwconfig;
198 	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
199 	u32 val;
200 
201 	init_final_memctl_regs();
202 
203 	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
204 
205 	env_hwconfig = getenv("hwconfig");
206 
207 	if (hwconfig_f("dspi", env_hwconfig) &&
208 	    DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
209 		config_board_mux(MUX_TYPE_DSPI);
210 	else
211 		config_board_mux(MUX_TYPE_SDHC);
212 
213 #if defined(CONFIG_NAND) && defined(CONFIG_FSL_QSPI)
214 	val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
215 
216 	if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
217 		QIXIS_WRITE(brdcfg[9],
218 			    (QIXIS_READ(brdcfg[9]) & 0xf8) |
219 			     FSL_QIXIS_BRDCFG9_QSPI);
220 #endif
221 
222 #ifdef CONFIG_ENV_IS_NOWHERE
223 	gd->env_addr = (ulong)&default_environment[0];
224 #endif
225 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
226 	rtc_enable_32khz_output();
227 
228 	return 0;
229 }
230 
231 int board_early_init_f(void)
232 {
233 #ifdef CONFIG_SYS_I2C_EARLY_INIT
234 	i2c_early_init_f();
235 #endif
236 	fsl_lsch3_early_init_f();
237 #ifdef CONFIG_FSL_QSPI
238 	/* input clk: 1/2 platform clk, output: input/20 */
239 	out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
240 #endif
241 	return 0;
242 }
243 
244 void detail_board_ddr_info(void)
245 {
246 	puts("\nDDR    ");
247 	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
248 	print_ddr_info(0);
249 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
250 	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
251 		puts("\nDP-DDR ");
252 		print_size(gd->bd->bi_dram[2].size, "");
253 		print_ddr_info(CONFIG_DP_DDR_CTRL);
254 	}
255 #endif
256 }
257 
258 int dram_init(void)
259 {
260 	gd->ram_size = initdram(0);
261 
262 	return 0;
263 }
264 
265 #if defined(CONFIG_ARCH_MISC_INIT)
266 int arch_misc_init(void)
267 {
268 #ifdef CONFIG_FSL_DEBUG_SERVER
269 	debug_server_init();
270 #endif
271 #ifdef CONFIG_FSL_CAAM
272 	sec_init();
273 #endif
274 	return 0;
275 }
276 #endif
277 
278 #ifdef CONFIG_FSL_MC_ENET
279 void fdt_fixup_board_enet(void *fdt)
280 {
281 	int offset;
282 
283 	offset = fdt_path_offset(fdt, "/soc/fsl-mc");
284 
285 	if (offset < 0)
286 		offset = fdt_path_offset(fdt, "/fsl-mc");
287 
288 	if (offset < 0) {
289 		printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
290 		       __func__, offset);
291 		return;
292 	}
293 
294 	if (get_mc_boot_status() == 0)
295 		fdt_status_okay(fdt, offset);
296 	else
297 		fdt_status_fail(fdt, offset);
298 }
299 #endif
300 
301 #ifdef CONFIG_OF_BOARD_SETUP
302 int ft_board_setup(void *blob, bd_t *bd)
303 {
304 #ifdef CONFIG_FSL_MC_ENET
305 	int err;
306 #endif
307 	u64 base[CONFIG_NR_DRAM_BANKS];
308 	u64 size[CONFIG_NR_DRAM_BANKS];
309 
310 	ft_cpu_setup(blob, bd);
311 
312 	/* fixup DT for the two GPP DDR banks */
313 	base[0] = gd->bd->bi_dram[0].start;
314 	size[0] = gd->bd->bi_dram[0].size;
315 	base[1] = gd->bd->bi_dram[1].start;
316 	size[1] = gd->bd->bi_dram[1].size;
317 
318 	fdt_fixup_memory_banks(blob, base, size, 2);
319 
320 	fdt_fixup_dr_usb(blob, bd);
321 
322 #ifdef CONFIG_FSL_MC_ENET
323 	fdt_fixup_board_enet(blob);
324 	err = fsl_mc_ldpaa_exit(bd);
325 	if (err)
326 		return err;
327 #endif
328 
329 	return 0;
330 }
331 #endif
332 
333 void qixis_dump_switch(void)
334 {
335 	int i, nr_of_cfgsw;
336 
337 	QIXIS_WRITE(cms[0], 0x00);
338 	nr_of_cfgsw = QIXIS_READ(cms[1]);
339 
340 	puts("DIP switch settings dump:\n");
341 	for (i = 1; i <= nr_of_cfgsw; i++) {
342 		QIXIS_WRITE(cms[0], i);
343 		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
344 	}
345 }
346