1 /*
2  * Copyright 2015 Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 #include <common.h>
7 #include <malloc.h>
8 #include <errno.h>
9 #include <netdev.h>
10 #include <fsl_ifc.h>
11 #include <fsl_ddr.h>
12 #include <asm/io.h>
13 #include <fdt_support.h>
14 #include <libfdt.h>
15 #include <fsl_debug_server.h>
16 #include <fsl-mc/fsl_mc.h>
17 #include <environment.h>
18 #include <i2c.h>
19 #include <rtc.h>
20 #include <asm/arch/soc.h>
21 #include <hwconfig.h>
22 #include <fsl_sec.h>
23 
24 #include "../common/qixis.h"
25 #include "ls2080aqds_qixis.h"
26 
27 #define PIN_MUX_SEL_SDHC	0x00
28 #define PIN_MUX_SEL_DSPI	0x0a
29 
30 #define SET_SDHC_MUX_SEL(reg, value)	((reg & 0xf0) | value)
31 
32 DECLARE_GLOBAL_DATA_PTR;
33 
34 enum {
35 	MUX_TYPE_SDHC,
36 	MUX_TYPE_DSPI,
37 };
38 
39 unsigned long long get_qixis_addr(void)
40 {
41 	unsigned long long addr;
42 
43 	if (gd->flags & GD_FLG_RELOC)
44 		addr = QIXIS_BASE_PHYS;
45 	else
46 		addr = QIXIS_BASE_PHYS_EARLY;
47 
48 	/*
49 	 * IFC address under 256MB is mapped to 0x30000000, any address above
50 	 * is mapped to 0x5_10000000 up to 4GB.
51 	 */
52 	addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
53 
54 	return addr;
55 }
56 
57 int checkboard(void)
58 {
59 	char buf[64];
60 	u8 sw;
61 	static const char *const freq[] = {"100", "125", "156.25",
62 					    "100 separate SSCG"};
63 	int clock;
64 
65 	cpu_name(buf);
66 	printf("Board: %s-QDS, ", buf);
67 
68 	sw = QIXIS_READ(arch);
69 	printf("Board Arch: V%d, ", sw >> 4);
70 	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
71 
72 	memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
73 
74 	sw = QIXIS_READ(brdcfg[0]);
75 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
76 
77 	if (sw < 0x8)
78 		printf("vBank: %d\n", sw);
79 	else if (sw == 0x8)
80 		puts("PromJet\n");
81 	else if (sw == 0x9)
82 		puts("NAND\n");
83 	else if (sw == 0x15)
84 		printf("IFCCard\n");
85 	else
86 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
87 
88 	printf("FPGA: v%d (%s), build %d",
89 	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
90 	       (int)qixis_read_minor());
91 	/* the timestamp string contains "\n" at the end */
92 	printf(" on %s", qixis_read_time(buf));
93 
94 	/*
95 	 * Display the actual SERDES reference clocks as configured by the
96 	 * dip switches on the board.  Note that the SWx registers could
97 	 * technically be set to force the reference clocks to match the
98 	 * values that the SERDES expects (or vice versa).  For now, however,
99 	 * we just display both values and hope the user notices when they
100 	 * don't match.
101 	 */
102 	puts("SERDES1 Reference : ");
103 	sw = QIXIS_READ(brdcfg[2]);
104 	clock = (sw >> 6) & 3;
105 	printf("Clock1 = %sMHz ", freq[clock]);
106 	clock = (sw >> 4) & 3;
107 	printf("Clock2 = %sMHz", freq[clock]);
108 
109 	puts("\nSERDES2 Reference : ");
110 	clock = (sw >> 2) & 3;
111 	printf("Clock1 = %sMHz ", freq[clock]);
112 	clock = (sw >> 0) & 3;
113 	printf("Clock2 = %sMHz\n", freq[clock]);
114 
115 	return 0;
116 }
117 
118 unsigned long get_board_sys_clk(void)
119 {
120 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
121 
122 	switch (sysclk_conf & 0x0F) {
123 	case QIXIS_SYSCLK_83:
124 		return 83333333;
125 	case QIXIS_SYSCLK_100:
126 		return 100000000;
127 	case QIXIS_SYSCLK_125:
128 		return 125000000;
129 	case QIXIS_SYSCLK_133:
130 		return 133333333;
131 	case QIXIS_SYSCLK_150:
132 		return 150000000;
133 	case QIXIS_SYSCLK_160:
134 		return 160000000;
135 	case QIXIS_SYSCLK_166:
136 		return 166666666;
137 	}
138 	return 66666666;
139 }
140 
141 unsigned long get_board_ddr_clk(void)
142 {
143 	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
144 
145 	switch ((ddrclk_conf & 0x30) >> 4) {
146 	case QIXIS_DDRCLK_100:
147 		return 100000000;
148 	case QIXIS_DDRCLK_125:
149 		return 125000000;
150 	case QIXIS_DDRCLK_133:
151 		return 133333333;
152 	}
153 	return 66666666;
154 }
155 
156 int select_i2c_ch_pca9547(u8 ch)
157 {
158 	int ret;
159 
160 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
161 	if (ret) {
162 		puts("PCA: failed to select proper channel\n");
163 		return ret;
164 	}
165 
166 	return 0;
167 }
168 
169 int config_board_mux(int ctrl_type)
170 {
171 	u8 reg5;
172 
173 	reg5 = QIXIS_READ(brdcfg[5]);
174 
175 	switch (ctrl_type) {
176 	case MUX_TYPE_SDHC:
177 		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
178 		break;
179 	case MUX_TYPE_DSPI:
180 		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
181 		break;
182 	default:
183 		printf("Wrong mux interface type\n");
184 		return -1;
185 	}
186 
187 	QIXIS_WRITE(brdcfg[5], reg5);
188 
189 	return 0;
190 }
191 
192 int board_init(void)
193 {
194 	char *env_hwconfig;
195 	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
196 	u32 val;
197 
198 	init_final_memctl_regs();
199 
200 	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
201 
202 	env_hwconfig = getenv("hwconfig");
203 
204 	if (hwconfig_f("dspi", env_hwconfig) &&
205 	    DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
206 		config_board_mux(MUX_TYPE_DSPI);
207 	else
208 		config_board_mux(MUX_TYPE_SDHC);
209 
210 #ifdef CONFIG_ENV_IS_NOWHERE
211 	gd->env_addr = (ulong)&default_environment[0];
212 #endif
213 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
214 	rtc_enable_32khz_output();
215 
216 	return 0;
217 }
218 
219 int board_early_init_f(void)
220 {
221 	fsl_lsch3_early_init_f();
222 	return 0;
223 }
224 
225 void detail_board_ddr_info(void)
226 {
227 	puts("\nDDR    ");
228 	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
229 	print_ddr_info(0);
230 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
231 	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
232 		puts("\nDP-DDR ");
233 		print_size(gd->bd->bi_dram[2].size, "");
234 		print_ddr_info(CONFIG_DP_DDR_CTRL);
235 	}
236 #endif
237 }
238 
239 int dram_init(void)
240 {
241 	gd->ram_size = initdram(0);
242 
243 	return 0;
244 }
245 
246 #if defined(CONFIG_ARCH_MISC_INIT)
247 int arch_misc_init(void)
248 {
249 #ifdef CONFIG_FSL_DEBUG_SERVER
250 	debug_server_init();
251 #endif
252 #ifdef CONFIG_FSL_CAAM
253 	sec_init();
254 #endif
255 	return 0;
256 }
257 #endif
258 
259 #ifdef CONFIG_FSL_MC_ENET
260 void fdt_fixup_board_enet(void *fdt)
261 {
262 	int offset;
263 
264 	offset = fdt_path_offset(fdt, "/soc/fsl-mc");
265 
266 	if (offset < 0)
267 		offset = fdt_path_offset(fdt, "/fsl-mc");
268 
269 	if (offset < 0) {
270 		printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
271 		       __func__, offset);
272 		return;
273 	}
274 
275 	if (get_mc_boot_status() == 0)
276 		fdt_status_okay(fdt, offset);
277 	else
278 		fdt_status_fail(fdt, offset);
279 }
280 #endif
281 
282 #ifdef CONFIG_OF_BOARD_SETUP
283 int ft_board_setup(void *blob, bd_t *bd)
284 {
285 #ifdef CONFIG_FSL_MC_ENET
286 	int err;
287 #endif
288 	u64 base[CONFIG_NR_DRAM_BANKS];
289 	u64 size[CONFIG_NR_DRAM_BANKS];
290 
291 	ft_cpu_setup(blob, bd);
292 
293 	/* fixup DT for the two GPP DDR banks */
294 	base[0] = gd->bd->bi_dram[0].start;
295 	size[0] = gd->bd->bi_dram[0].size;
296 	base[1] = gd->bd->bi_dram[1].start;
297 	size[1] = gd->bd->bi_dram[1].size;
298 
299 	fdt_fixup_memory_banks(blob, base, size, 2);
300 
301 #ifdef CONFIG_FSL_MC_ENET
302 	fdt_fixup_board_enet(blob);
303 	err = fsl_mc_ldpaa_exit(bd);
304 	if (err)
305 		return err;
306 #endif
307 
308 	return 0;
309 }
310 #endif
311 
312 void qixis_dump_switch(void)
313 {
314 	int i, nr_of_cfgsw;
315 
316 	QIXIS_WRITE(cms[0], 0x00);
317 	nr_of_cfgsw = QIXIS_READ(cms[1]);
318 
319 	puts("DIP switch settings dump:\n");
320 	for (i = 1; i <= nr_of_cfgsw; i++) {
321 		QIXIS_WRITE(cms[0], i);
322 		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
323 	}
324 }
325