1 /*
2  * Copyright 2015 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <netdev.h>
9 #include <asm/io.h>
10 #include <asm/arch/fsl_serdes.h>
11 #include <hwconfig.h>
12 #include <fsl_mdio.h>
13 #include <malloc.h>
14 #include <fm_eth.h>
15 #include <i2c.h>
16 #include <miiphy.h>
17 #include <fsl-mc/ldpaa_wriop.h>
18 
19 #include "../common/qixis.h"
20 
21 #include "ls2080aqds_qixis.h"
22 
23 
24 #ifdef CONFIG_FSL_MC_ENET
25  /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
26  *   Bank 1 -> Lanes A, B, C, D, E, F, G, H
27  *   Bank 2 -> Lanes A,B, C, D, E, F, G, H
28  */
29 
30  /* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here
31   * means that the mapping must be determined dynamically, or that the lane
32   * maps to something other than a board slot.
33   */
34 
35 static u8 lane_to_slot_fsm1[] = {
36 	0, 0, 0, 0, 0, 0, 0, 0
37 };
38 
39 static u8 lane_to_slot_fsm2[] = {
40 	0, 0, 0, 0, 0, 0, 0, 0
41 };
42 
43 /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
44  * housed.
45  */
46 
47 static int xqsgii_riser_phy_addr[] = {
48 	XQSGMII_CARD_PHY1_PORT0_ADDR,
49 	XQSGMII_CARD_PHY2_PORT0_ADDR,
50 	XQSGMII_CARD_PHY3_PORT0_ADDR,
51 	XQSGMII_CARD_PHY4_PORT0_ADDR,
52 	XQSGMII_CARD_PHY3_PORT2_ADDR,
53 	XQSGMII_CARD_PHY1_PORT2_ADDR,
54 	XQSGMII_CARD_PHY4_PORT2_ADDR,
55 	XQSGMII_CARD_PHY2_PORT2_ADDR,
56 };
57 
58 static int sgmii_riser_phy_addr[] = {
59 	SGMII_CARD_PORT1_PHY_ADDR,
60 	SGMII_CARD_PORT2_PHY_ADDR,
61 	SGMII_CARD_PORT3_PHY_ADDR,
62 	SGMII_CARD_PORT4_PHY_ADDR,
63 };
64 
65 /* Slot2 does not have EMI connections */
66 #define EMI_NONE	0xFFFFFFFF
67 #define EMI1_SLOT1	0
68 #define EMI1_SLOT2	1
69 #define EMI1_SLOT3	2
70 #define EMI1_SLOT4	3
71 #define EMI1_SLOT5	4
72 #define EMI1_SLOT6	5
73 #define EMI2		6
74 #define SFP_TX		0
75 
76 static const char * const mdio_names[] = {
77 	"LS2080A_QDS_MDIO0",
78 	"LS2080A_QDS_MDIO1",
79 	"LS2080A_QDS_MDIO2",
80 	"LS2080A_QDS_MDIO3",
81 	"LS2080A_QDS_MDIO4",
82 	"LS2080A_QDS_MDIO5",
83 	DEFAULT_WRIOP_MDIO2_NAME,
84 };
85 
86 struct ls2080a_qds_mdio {
87 	u8 muxval;
88 	struct mii_dev *realbus;
89 };
90 
91 static void sgmii_configure_repeater(int serdes_port)
92 {
93 	struct mii_dev *bus;
94 	uint8_t a = 0xf;
95 	int i, j, ret;
96 	int dpmac_id = 0, dpmac, mii_bus = 0;
97 	unsigned short value;
98 	char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
99 	uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60};
100 
101 	uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
102 	uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
103 	uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
104 	uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
105 
106 	int *riser_phy_addr = &xqsgii_riser_phy_addr[0];
107 
108 	/* Set I2c to Slot 1 */
109 	i2c_write(0x77, 0, 0, &a, 1);
110 
111 	for (dpmac = 0; dpmac < 8; dpmac++) {
112 		/* Check the PHY status */
113 		switch (serdes_port) {
114 		case 1:
115 			mii_bus = 0;
116 			dpmac_id = dpmac + 1;
117 			break;
118 		case 2:
119 			mii_bus = 1;
120 			dpmac_id = dpmac + 9;
121 			a = 0xb;
122 			i2c_write(0x76, 0, 0, &a, 1);
123 			break;
124 		}
125 
126 		ret = miiphy_set_current_dev(dev[mii_bus]);
127 		if (ret > 0)
128 			goto error;
129 
130 		bus = mdio_get_current_dev();
131 		debug("Reading from bus %s\n", bus->name);
132 
133 		ret = miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f,
134 				   3);
135 		if (ret > 0)
136 			goto error;
137 
138 		mdelay(10);
139 		ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], 0x11,
140 				  &value);
141 		if (ret > 0)
142 			goto error;
143 
144 		mdelay(10);
145 
146 		if ((value & 0xfff) == 0x40f) {
147 			printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id);
148 			continue;
149 		}
150 
151 		for (i = 0; i < 4; i++) {
152 			for (j = 0; j < 4; j++) {
153 				a = 0x18;
154 				i2c_write(i2c_addr[dpmac], 6, 1, &a, 1);
155 				a = 0x38;
156 				i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
157 				a = 0x4;
158 				i2c_write(i2c_addr[dpmac], 8, 1, &a, 1);
159 
160 				i2c_write(i2c_addr[dpmac], 0xf, 1,
161 					  &ch_a_eq[i], 1);
162 				i2c_write(i2c_addr[dpmac], 0x11, 1,
163 					  &ch_a_ctl2[j], 1);
164 
165 				i2c_write(i2c_addr[dpmac], 0x16, 1,
166 					  &ch_b_eq[i], 1);
167 				i2c_write(i2c_addr[dpmac], 0x18, 1,
168 					  &ch_b_ctl2[j], 1);
169 
170 				a = 0x14;
171 				i2c_write(i2c_addr[dpmac], 0x23, 1, &a, 1);
172 				a = 0xb5;
173 				i2c_write(i2c_addr[dpmac], 0x2d, 1, &a, 1);
174 				a = 0x20;
175 				i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
176 				mdelay(100);
177 				ret = miiphy_read(dev[mii_bus],
178 						  riser_phy_addr[dpmac],
179 						  0x11, &value);
180 				if (ret > 0)
181 					goto error;
182 
183 				mdelay(1);
184 				ret = miiphy_read(dev[mii_bus],
185 						  riser_phy_addr[dpmac],
186 						  0x11, &value);
187 				if (ret > 0)
188 					goto error;
189 				mdelay(10);
190 
191 				if ((value & 0xfff) == 0x40f) {
192 					printf("DPMAC %d :PHY is configured ",
193 					       dpmac_id);
194 					printf("after setting repeater 0x%x\n",
195 					       value);
196 					i = 5;
197 					j = 5;
198 				} else
199 					printf("DPMAC %d :PHY is failed to ",
200 					       dpmac_id);
201 					printf("configure the repeater 0x%x\n",
202 					       value);
203 				}
204 		}
205 	}
206 error:
207 	if (ret)
208 		printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac_id);
209 	return;
210 }
211 
212 static void qsgmii_configure_repeater(int dpmac)
213 {
214 	uint8_t a = 0xf;
215 	int i, j;
216 	int i2c_phy_addr = 0;
217 	int phy_addr = 0;
218 	int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
219 
220 	uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
221 	uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
222 	uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
223 	uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
224 
225 	const char *dev = "LS2080A_QDS_MDIO0";
226 	int ret = 0;
227 	unsigned short value;
228 
229 	/* Set I2c to Slot 1 */
230 	i2c_write(0x77, 0, 0, &a, 1);
231 
232 	switch (dpmac) {
233 	case 1:
234 	case 2:
235 	case 3:
236 	case 4:
237 		i2c_phy_addr = i2c_addr[0];
238 		phy_addr = 0;
239 		break;
240 
241 	case 5:
242 	case 6:
243 	case 7:
244 	case 8:
245 		i2c_phy_addr = i2c_addr[1];
246 		phy_addr = 4;
247 		break;
248 
249 	case 9:
250 	case 10:
251 	case 11:
252 	case 12:
253 		i2c_phy_addr = i2c_addr[2];
254 		phy_addr = 8;
255 		break;
256 
257 	case 13:
258 	case 14:
259 	case 15:
260 	case 16:
261 		i2c_phy_addr = i2c_addr[3];
262 		phy_addr = 0xc;
263 		break;
264 	}
265 
266 	/* Check the PHY status */
267 	ret = miiphy_set_current_dev(dev);
268 	ret = miiphy_write(dev, phy_addr, 0x1f, 3);
269 	mdelay(10);
270 	ret = miiphy_read(dev, phy_addr, 0x11, &value);
271 	mdelay(10);
272 	ret = miiphy_read(dev, phy_addr, 0x11, &value);
273 	mdelay(10);
274 	if ((value & 0xf) == 0xf) {
275 		printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
276 		return;
277 	}
278 
279 	for (i = 0; i < 4; i++) {
280 		for (j = 0; j < 4; j++) {
281 			a = 0x18;
282 			i2c_write(i2c_phy_addr, 6, 1, &a, 1);
283 			a = 0x38;
284 			i2c_write(i2c_phy_addr, 4, 1, &a, 1);
285 			a = 0x4;
286 			i2c_write(i2c_phy_addr, 8, 1, &a, 1);
287 
288 			i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
289 			i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);
290 
291 			i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
292 			i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);
293 
294 			a = 0x14;
295 			i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
296 			a = 0xb5;
297 			i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
298 			a = 0x20;
299 			i2c_write(i2c_phy_addr, 4, 1, &a, 1);
300 			mdelay(100);
301 			ret = miiphy_read(dev, phy_addr, 0x11, &value);
302 			if (ret > 0)
303 				goto error;
304 			mdelay(1);
305 			ret = miiphy_read(dev, phy_addr, 0x11, &value);
306 			if (ret > 0)
307 				goto error;
308 			mdelay(10);
309 			if ((value & 0xf) == 0xf) {
310 				printf("DPMAC %d :PHY is ..... Configured\n",
311 				       dpmac);
312 				return;
313 			}
314 		}
315 	}
316 error:
317 	printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
318 	return;
319 }
320 
321 static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval)
322 {
323 	return mdio_names[muxval];
324 }
325 
326 struct mii_dev *mii_dev_for_muxval(u8 muxval)
327 {
328 	struct mii_dev *bus;
329 	const char *name = ls2080a_qds_mdio_name_for_muxval(muxval);
330 
331 	if (!name) {
332 		printf("No bus for muxval %x\n", muxval);
333 		return NULL;
334 	}
335 
336 	bus = miiphy_get_dev_by_name(name);
337 
338 	if (!bus) {
339 		printf("No bus by name %s\n", name);
340 		return NULL;
341 	}
342 
343 	return bus;
344 }
345 
346 static void ls2080a_qds_enable_SFP_TX(u8 muxval)
347 {
348 	u8 brdcfg9;
349 
350 	brdcfg9 = QIXIS_READ(brdcfg[9]);
351 	brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
352 	brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
353 	QIXIS_WRITE(brdcfg[9], brdcfg9);
354 }
355 
356 static void ls2080a_qds_mux_mdio(u8 muxval)
357 {
358 	u8 brdcfg4;
359 
360 	if (muxval <= 5) {
361 		brdcfg4 = QIXIS_READ(brdcfg[4]);
362 		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
363 		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
364 		QIXIS_WRITE(brdcfg[4], brdcfg4);
365 	}
366 }
367 
368 static int ls2080a_qds_mdio_read(struct mii_dev *bus, int addr,
369 				 int devad, int regnum)
370 {
371 	struct ls2080a_qds_mdio *priv = bus->priv;
372 
373 	ls2080a_qds_mux_mdio(priv->muxval);
374 
375 	return priv->realbus->read(priv->realbus, addr, devad, regnum);
376 }
377 
378 static int ls2080a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
379 				  int regnum, u16 value)
380 {
381 	struct ls2080a_qds_mdio *priv = bus->priv;
382 
383 	ls2080a_qds_mux_mdio(priv->muxval);
384 
385 	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
386 }
387 
388 static int ls2080a_qds_mdio_reset(struct mii_dev *bus)
389 {
390 	struct ls2080a_qds_mdio *priv = bus->priv;
391 
392 	return priv->realbus->reset(priv->realbus);
393 }
394 
395 static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval)
396 {
397 	struct ls2080a_qds_mdio *pmdio;
398 	struct mii_dev *bus = mdio_alloc();
399 
400 	if (!bus) {
401 		printf("Failed to allocate ls2080a_qds MDIO bus\n");
402 		return -1;
403 	}
404 
405 	pmdio = malloc(sizeof(*pmdio));
406 	if (!pmdio) {
407 		printf("Failed to allocate ls2080a_qds private data\n");
408 		free(bus);
409 		return -1;
410 	}
411 
412 	bus->read = ls2080a_qds_mdio_read;
413 	bus->write = ls2080a_qds_mdio_write;
414 	bus->reset = ls2080a_qds_mdio_reset;
415 	strcpy(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval));
416 
417 	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
418 
419 	if (!pmdio->realbus) {
420 		printf("No bus with name %s\n", realbusname);
421 		free(bus);
422 		free(pmdio);
423 		return -1;
424 	}
425 
426 	pmdio->muxval = muxval;
427 	bus->priv = pmdio;
428 
429 	return mdio_register(bus);
430 }
431 
432 /*
433  * Initialize the dpmac_info array.
434  *
435  */
436 static void initialize_dpmac_to_slot(void)
437 {
438 	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
439 	int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
440 				FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
441 		>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
442 	int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
443 				FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
444 		>> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
445 
446 	char *env_hwconfig;
447 	env_hwconfig = getenv("hwconfig");
448 
449 	switch (serdes1_prtcl) {
450 	case 0x07:
451 	case 0x09:
452 	case 0x33:
453 		printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
454 		       serdes1_prtcl);
455 		lane_to_slot_fsm1[0] = EMI1_SLOT1;
456 		lane_to_slot_fsm1[1] = EMI1_SLOT1;
457 		lane_to_slot_fsm1[2] = EMI1_SLOT1;
458 		lane_to_slot_fsm1[3] = EMI1_SLOT1;
459 		if (hwconfig_f("xqsgmii", env_hwconfig)) {
460 			lane_to_slot_fsm1[4] = EMI1_SLOT1;
461 			lane_to_slot_fsm1[5] = EMI1_SLOT1;
462 			lane_to_slot_fsm1[6] = EMI1_SLOT1;
463 			lane_to_slot_fsm1[7] = EMI1_SLOT1;
464 		} else {
465 			lane_to_slot_fsm1[4] = EMI1_SLOT2;
466 			lane_to_slot_fsm1[5] = EMI1_SLOT2;
467 			lane_to_slot_fsm1[6] = EMI1_SLOT2;
468 			lane_to_slot_fsm1[7] = EMI1_SLOT2;
469 		}
470 		break;
471 
472 	case 0x2A:
473 		printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
474 		       serdes1_prtcl);
475 		break;
476 	default:
477 		printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
478 		       __func__, serdes1_prtcl);
479 		break;
480 	}
481 
482 	switch (serdes2_prtcl) {
483 	case 0x07:
484 	case 0x08:
485 	case 0x09:
486 	case 0x49:
487 		printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
488 		       serdes2_prtcl);
489 		lane_to_slot_fsm2[0] = EMI1_SLOT4;
490 		lane_to_slot_fsm2[1] = EMI1_SLOT4;
491 		lane_to_slot_fsm2[2] = EMI1_SLOT4;
492 		lane_to_slot_fsm2[3] = EMI1_SLOT4;
493 
494 		if (hwconfig_f("xqsgmii", env_hwconfig)) {
495 			lane_to_slot_fsm2[4] = EMI1_SLOT4;
496 			lane_to_slot_fsm2[5] = EMI1_SLOT4;
497 			lane_to_slot_fsm2[6] = EMI1_SLOT4;
498 			lane_to_slot_fsm2[7] = EMI1_SLOT4;
499 		} else {
500 			/* No MDIO physical connection */
501 			lane_to_slot_fsm2[4] = EMI1_SLOT6;
502 			lane_to_slot_fsm2[5] = EMI1_SLOT6;
503 			lane_to_slot_fsm2[6] = EMI1_SLOT6;
504 			lane_to_slot_fsm2[7] = EMI1_SLOT6;
505 		}
506 		break;
507 	default:
508 		printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
509 		       __func__ , serdes2_prtcl);
510 		break;
511 	}
512 }
513 
514 void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
515 {
516 	int lane, slot;
517 	struct mii_dev *bus;
518 	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
519 	int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
520 				FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
521 		>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
522 	int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
523 				FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
524 		>> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
525 
526 	int *riser_phy_addr;
527 	char *env_hwconfig = getenv("hwconfig");
528 
529 	if (hwconfig_f("xqsgmii", env_hwconfig))
530 		riser_phy_addr = &xqsgii_riser_phy_addr[0];
531 	else
532 		riser_phy_addr = &sgmii_riser_phy_addr[0];
533 
534 	if (dpmac_id > WRIOP1_DPMAC9)
535 		goto serdes2;
536 
537 	switch (serdes1_prtcl) {
538 	case 0x07:
539 
540 		lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id);
541 		slot = lane_to_slot_fsm1[lane];
542 
543 		switch (++slot) {
544 		case 1:
545 			/* Slot housing a SGMII riser card? */
546 			wriop_set_phy_address(dpmac_id,
547 					      riser_phy_addr[dpmac_id - 1]);
548 			dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
549 			bus = mii_dev_for_muxval(EMI1_SLOT1);
550 			wriop_set_mdio(dpmac_id, bus);
551 			dpmac_info[dpmac_id].phydev = phy_connect(
552 						dpmac_info[dpmac_id].bus,
553 						dpmac_info[dpmac_id].phy_addr,
554 						NULL,
555 						dpmac_info[dpmac_id].enet_if);
556 			phy_config(dpmac_info[dpmac_id].phydev);
557 			break;
558 		case 2:
559 			/* Slot housing a SGMII riser card? */
560 			wriop_set_phy_address(dpmac_id,
561 					      riser_phy_addr[dpmac_id - 1]);
562 			dpmac_info[dpmac_id].board_mux = EMI1_SLOT2;
563 			bus = mii_dev_for_muxval(EMI1_SLOT2);
564 			wriop_set_mdio(dpmac_id, bus);
565 			dpmac_info[dpmac_id].phydev = phy_connect(
566 						dpmac_info[dpmac_id].bus,
567 						dpmac_info[dpmac_id].phy_addr,
568 						NULL,
569 						dpmac_info[dpmac_id].enet_if);
570 			phy_config(dpmac_info[dpmac_id].phydev);
571 			break;
572 		case 3:
573 			break;
574 		case 4:
575 			break;
576 		case 5:
577 			break;
578 		case 6:
579 			break;
580 		}
581 	break;
582 	default:
583 		printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
584 		       __func__ , serdes1_prtcl);
585 	break;
586 	}
587 
588 serdes2:
589 	switch (serdes2_prtcl) {
590 	case 0x07:
591 	case 0x08:
592 	case 0x49:
593 		lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
594 							(dpmac_id - 9));
595 		slot = lane_to_slot_fsm2[lane];
596 
597 		switch (++slot) {
598 		case 1:
599 			break;
600 		case 3:
601 			break;
602 		case 4:
603 			/* Slot housing a SGMII riser card? */
604 			wriop_set_phy_address(dpmac_id,
605 					      riser_phy_addr[dpmac_id - 9]);
606 			dpmac_info[dpmac_id].board_mux = EMI1_SLOT4;
607 			bus = mii_dev_for_muxval(EMI1_SLOT4);
608 			wriop_set_mdio(dpmac_id, bus);
609 			dpmac_info[dpmac_id].phydev = phy_connect(
610 						dpmac_info[dpmac_id].bus,
611 						dpmac_info[dpmac_id].phy_addr,
612 						NULL,
613 						dpmac_info[dpmac_id].enet_if);
614 			phy_config(dpmac_info[dpmac_id].phydev);
615 		break;
616 		case 5:
617 		break;
618 		case 6:
619 			/* Slot housing a SGMII riser card? */
620 			wriop_set_phy_address(dpmac_id,
621 					      riser_phy_addr[dpmac_id - 13]);
622 			dpmac_info[dpmac_id].board_mux = EMI1_SLOT6;
623 			bus = mii_dev_for_muxval(EMI1_SLOT6);
624 			wriop_set_mdio(dpmac_id, bus);
625 		break;
626 	}
627 	break;
628 	default:
629 		printf("%s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
630 		       __func__, serdes2_prtcl);
631 	break;
632 	}
633 }
634 
635 void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
636 {
637 	int lane = 0, slot;
638 	struct mii_dev *bus;
639 	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
640 	int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
641 				FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
642 		>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
643 
644 	switch (serdes1_prtcl) {
645 	case 0x33:
646 		switch (dpmac_id) {
647 		case 1:
648 		case 2:
649 		case 3:
650 		case 4:
651 			lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_A);
652 		break;
653 		case 5:
654 		case 6:
655 		case 7:
656 		case 8:
657 			lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_B);
658 		break;
659 		case 9:
660 		case 10:
661 		case 11:
662 		case 12:
663 			lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_C);
664 		break;
665 		case 13:
666 		case 14:
667 		case 15:
668 		case 16:
669 			lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_D);
670 		break;
671 	}
672 
673 		slot = lane_to_slot_fsm1[lane];
674 
675 		switch (++slot) {
676 		case 1:
677 			/* Slot housing a QSGMII riser card? */
678 			wriop_set_phy_address(dpmac_id, dpmac_id - 1);
679 			dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
680 			bus = mii_dev_for_muxval(EMI1_SLOT1);
681 			wriop_set_mdio(dpmac_id, bus);
682 			dpmac_info[dpmac_id].phydev = phy_connect(
683 						dpmac_info[dpmac_id].bus,
684 						dpmac_info[dpmac_id].phy_addr,
685 						NULL,
686 						dpmac_info[dpmac_id].enet_if);
687 
688 			phy_config(dpmac_info[dpmac_id].phydev);
689 			break;
690 		case 3:
691 			break;
692 		case 4:
693 			break;
694 		case 5:
695 		break;
696 		case 6:
697 			break;
698 	}
699 	break;
700 	default:
701 		printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
702 		       serdes1_prtcl);
703 	break;
704 	}
705 
706 	qsgmii_configure_repeater(dpmac_id);
707 }
708 
709 void ls2080a_handle_phy_interface_xsgmii(int i)
710 {
711 	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
712 	int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
713 				FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
714 		>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
715 
716 	switch (serdes1_prtcl) {
717 	case 0x2A:
718 		/*
719 		 * XFI does not need a PHY to work, but to avoid U-Boot use
720 		 * default PHY address which is zero to a MAC when it found
721 		 * a MAC has no PHY address, we give a PHY address to XFI
722 		 * MAC, and should not use a real XAUI PHY address, since
723 		 * MDIO can access it successfully, and then MDIO thinks
724 		 * the XAUI card is used for the XFI MAC, which will cause
725 		 * error.
726 		 */
727 		wriop_set_phy_address(i, i + 4);
728 		ls2080a_qds_enable_SFP_TX(SFP_TX);
729 
730 		break;
731 	default:
732 		printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
733 		       serdes1_prtcl);
734 		break;
735 	}
736 }
737 #endif
738 
739 int board_eth_init(bd_t *bis)
740 {
741 	int error;
742 #ifdef CONFIG_FSL_MC_ENET
743 	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
744 	int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
745 				FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
746 		>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
747 	int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
748 				FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
749 		>> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
750 
751 	struct memac_mdio_info *memac_mdio0_info;
752 	struct memac_mdio_info *memac_mdio1_info;
753 	unsigned int i;
754 	char *env_hwconfig;
755 
756 	env_hwconfig = getenv("hwconfig");
757 
758 	initialize_dpmac_to_slot();
759 
760 	memac_mdio0_info = (struct memac_mdio_info *)malloc(
761 					sizeof(struct memac_mdio_info));
762 	memac_mdio0_info->regs =
763 		(struct memac_mdio_controller *)
764 					CONFIG_SYS_FSL_WRIOP1_MDIO1;
765 	memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
766 
767 	/* Register the real MDIO1 bus */
768 	fm_memac_mdio_init(bis, memac_mdio0_info);
769 
770 	memac_mdio1_info = (struct memac_mdio_info *)malloc(
771 					sizeof(struct memac_mdio_info));
772 	memac_mdio1_info->regs =
773 		(struct memac_mdio_controller *)
774 					CONFIG_SYS_FSL_WRIOP1_MDIO2;
775 	memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
776 
777 	/* Register the real MDIO2 bus */
778 	fm_memac_mdio_init(bis, memac_mdio1_info);
779 
780 	/* Register the muxing front-ends to the MDIO buses */
781 	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
782 	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
783 	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
784 	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
785 	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
786 	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
787 
788 	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
789 
790 	for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
791 		switch (wriop_get_enet_if(i)) {
792 		case PHY_INTERFACE_MODE_QSGMII:
793 			ls2080a_handle_phy_interface_qsgmii(i);
794 			break;
795 		case PHY_INTERFACE_MODE_SGMII:
796 			ls2080a_handle_phy_interface_sgmii(i);
797 			break;
798 		case PHY_INTERFACE_MODE_XGMII:
799 			ls2080a_handle_phy_interface_xsgmii(i);
800 			break;
801 		default:
802 			break;
803 
804 		if (i == 16)
805 			i = NUM_WRIOP_PORTS;
806 		}
807 	}
808 
809 	error = cpu_eth_init(bis);
810 
811 	if (hwconfig_f("xqsgmii", env_hwconfig)) {
812 		if (serdes1_prtcl == 0x7)
813 			sgmii_configure_repeater(1);
814 		if (serdes2_prtcl == 0x7 || serdes2_prtcl == 0x8 ||
815 		    serdes2_prtcl == 0x49)
816 			sgmii_configure_repeater(2);
817 	}
818 #endif
819 	error = pci_eth_init(bis);
820 	return error;
821 }
822 
823 #ifdef CONFIG_FSL_MC_ENET
824 
825 #endif
826