1 /* 2 * Copyright 2014 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <malloc.h> 8 #include <errno.h> 9 #include <netdev.h> 10 #include <fsl_ifc.h> 11 #include <fsl_ddr.h> 12 #include <asm/io.h> 13 #include <fdt_support.h> 14 #include <libfdt.h> 15 #include <fsl-mc/fsl_mc.h> 16 #include <environment.h> 17 #include <asm/arch/soc.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 int board_init(void) 22 { 23 init_final_memctl_regs(); 24 25 #ifdef CONFIG_ENV_IS_NOWHERE 26 gd->env_addr = (ulong)&default_environment[0]; 27 #endif 28 29 return 0; 30 } 31 32 int board_early_init_f(void) 33 { 34 fsl_lsch3_early_init_f(); 35 return 0; 36 } 37 38 void detail_board_ddr_info(void) 39 { 40 puts("\nDDR "); 41 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); 42 print_ddr_info(0); 43 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 44 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { 45 puts("\nDP-DDR "); 46 print_size(gd->bd->bi_dram[2].size, ""); 47 print_ddr_info(CONFIG_DP_DDR_CTRL); 48 } 49 #endif 50 } 51 52 #if defined(CONFIG_ARCH_MISC_INIT) 53 int arch_misc_init(void) 54 { 55 return 0; 56 } 57 #endif 58 59 int board_eth_init(bd_t *bis) 60 { 61 int error = 0; 62 63 #ifdef CONFIG_SMC91111 64 error = smc91111_initialize(0, CONFIG_SMC91111_BASE); 65 #endif 66 67 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) 68 error = cpu_eth_init(bis); 69 #endif 70 return error; 71 } 72 73 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) 74 void fdt_fixup_board_enet(void *fdt) 75 { 76 int offset; 77 78 offset = fdt_path_offset(fdt, "/soc/fsl-mc"); 79 80 /* 81 * TODO: Remove this when backward compatibility 82 * with old DT node (/fsl-mc) is no longer needed. 83 */ 84 if (offset < 0) 85 offset = fdt_path_offset(fdt, "/fsl-mc"); 86 87 if (offset < 0) { 88 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", 89 __func__, offset); 90 return; 91 } 92 93 if (get_mc_boot_status() == 0) 94 fdt_status_okay(fdt, offset); 95 else 96 fdt_status_fail(fdt, offset); 97 } 98 99 void board_quiesce_devices(void) 100 { 101 fsl_mc_ldpaa_exit(gd->bd); 102 } 103 #endif 104 105 #ifdef CONFIG_OF_BOARD_SETUP 106 int ft_board_setup(void *blob, bd_t *bd) 107 { 108 u64 base[CONFIG_NR_DRAM_BANKS]; 109 u64 size[CONFIG_NR_DRAM_BANKS]; 110 111 ft_cpu_setup(blob, bd); 112 113 /* fixup DT for the two GPP DDR banks */ 114 base[0] = gd->bd->bi_dram[0].start; 115 size[0] = gd->bd->bi_dram[0].size; 116 base[1] = gd->bd->bi_dram[1].start; 117 size[1] = gd->bd->bi_dram[1].size; 118 119 #ifdef CONFIG_RESV_RAM 120 /* reduce size if reserved memory is within this bank */ 121 if (gd->arch.resv_ram >= base[0] && 122 gd->arch.resv_ram < base[0] + size[0]) 123 size[0] = gd->arch.resv_ram - base[0]; 124 else if (gd->arch.resv_ram >= base[1] && 125 gd->arch.resv_ram < base[1] + size[1]) 126 size[1] = gd->arch.resv_ram - base[1]; 127 #endif 128 129 fdt_fixup_memory_banks(blob, base, size, 2); 130 131 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) 132 fdt_fixup_board_enet(blob); 133 #endif 134 135 return 0; 136 } 137 #endif 138 139 #if defined(CONFIG_RESET_PHY_R) 140 void reset_phy(void) 141 { 142 } 143 #endif 144