1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2014 Freescale Semiconductor
4  */
5 #include <common.h>
6 #include <malloc.h>
7 #include <errno.h>
8 #include <netdev.h>
9 #include <fsl_ifc.h>
10 #include <fsl_ddr.h>
11 #include <asm/io.h>
12 #include <fdt_support.h>
13 #include <linux/libfdt.h>
14 #include <fsl-mc/fsl_mc.h>
15 #include <environment.h>
16 #include <asm/arch/soc.h>
17 
18 DECLARE_GLOBAL_DATA_PTR;
19 
20 int board_init(void)
21 {
22 	init_final_memctl_regs();
23 
24 #ifdef CONFIG_ENV_IS_NOWHERE
25 	gd->env_addr = (ulong)&default_environment[0];
26 #endif
27 
28 	return 0;
29 }
30 
31 int board_early_init_f(void)
32 {
33 	fsl_lsch3_early_init_f();
34 	return 0;
35 }
36 
37 void detail_board_ddr_info(void)
38 {
39 	puts("\nDDR    ");
40 	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
41 	print_ddr_info(0);
42 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
43 	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
44 		puts("\nDP-DDR ");
45 		print_size(gd->bd->bi_dram[2].size, "");
46 		print_ddr_info(CONFIG_DP_DDR_CTRL);
47 	}
48 #endif
49 }
50 
51 #if defined(CONFIG_ARCH_MISC_INIT)
52 int arch_misc_init(void)
53 {
54 	return 0;
55 }
56 #endif
57 
58 int board_eth_init(bd_t *bis)
59 {
60 	int error = 0;
61 
62 #ifdef CONFIG_SMC91111
63 	error = smc91111_initialize(0, CONFIG_SMC91111_BASE);
64 #endif
65 
66 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
67 	error = cpu_eth_init(bis);
68 #endif
69 	return error;
70 }
71 
72 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
73 void fdt_fixup_board_enet(void *fdt)
74 {
75 	int offset;
76 
77 	offset = fdt_path_offset(fdt, "/soc/fsl-mc");
78 
79 	/*
80 	 * TODO: Remove this when backward compatibility
81 	 * with old DT node (/fsl-mc) is no longer needed.
82 	 */
83 	if (offset < 0)
84 		offset = fdt_path_offset(fdt, "/fsl-mc");
85 
86 	if (offset < 0) {
87 		printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
88 		       __func__, offset);
89 		return;
90 	}
91 
92 	if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
93 		fdt_status_okay(fdt, offset);
94 	else
95 		fdt_status_fail(fdt, offset);
96 }
97 
98 void board_quiesce_devices(void)
99 {
100 	fsl_mc_ldpaa_exit(gd->bd);
101 }
102 #endif
103 
104 #ifdef CONFIG_OF_BOARD_SETUP
105 int ft_board_setup(void *blob, bd_t *bd)
106 {
107 	u64 base[CONFIG_NR_DRAM_BANKS];
108 	u64 size[CONFIG_NR_DRAM_BANKS];
109 
110 	ft_cpu_setup(blob, bd);
111 
112 	/* fixup DT for the two GPP DDR banks */
113 	base[0] = gd->bd->bi_dram[0].start;
114 	size[0] = gd->bd->bi_dram[0].size;
115 	base[1] = gd->bd->bi_dram[1].start;
116 	size[1] = gd->bd->bi_dram[1].size;
117 
118 #ifdef CONFIG_RESV_RAM
119 	/* reduce size if reserved memory is within this bank */
120 	if (gd->arch.resv_ram >= base[0] &&
121 	    gd->arch.resv_ram < base[0] + size[0])
122 		size[0] = gd->arch.resv_ram - base[0];
123 	else if (gd->arch.resv_ram >= base[1] &&
124 		 gd->arch.resv_ram < base[1] + size[1])
125 		size[1] = gd->arch.resv_ram - base[1];
126 #endif
127 
128 	fdt_fixup_memory_banks(blob, base, size, 2);
129 
130 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
131 	fdt_fixup_board_enet(blob);
132 #endif
133 
134 	return 0;
135 }
136 #endif
137 
138 #if defined(CONFIG_RESET_PHY_R)
139 void reset_phy(void)
140 {
141 }
142 #endif
143