1 /* 2 * Copyright 2014 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <malloc.h> 8 #include <errno.h> 9 #include <netdev.h> 10 #include <fsl_ifc.h> 11 #include <fsl_ddr.h> 12 #include <asm/io.h> 13 #include <fdt_support.h> 14 #include <libfdt.h> 15 #include <fsl_debug_server.h> 16 #include <fsl-mc/fsl_mc.h> 17 #include <environment.h> 18 #include <asm/arch/soc.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 int board_init(void) 23 { 24 init_final_memctl_regs(); 25 26 #ifdef CONFIG_ENV_IS_NOWHERE 27 gd->env_addr = (ulong)&default_environment[0]; 28 #endif 29 30 return 0; 31 } 32 33 int board_early_init_f(void) 34 { 35 fsl_lsch3_early_init_f(); 36 return 0; 37 } 38 39 void detail_board_ddr_info(void) 40 { 41 puts("\nDDR "); 42 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); 43 print_ddr_info(0); 44 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 45 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { 46 puts("\nDP-DDR "); 47 print_size(gd->bd->bi_dram[2].size, ""); 48 print_ddr_info(CONFIG_DP_DDR_CTRL); 49 } 50 #endif 51 } 52 53 int dram_init(void) 54 { 55 gd->ram_size = initdram(0); 56 57 return 0; 58 } 59 60 #if defined(CONFIG_ARCH_MISC_INIT) 61 int arch_misc_init(void) 62 { 63 #ifdef CONFIG_FSL_DEBUG_SERVER 64 debug_server_init(); 65 #endif 66 67 return 0; 68 } 69 #endif 70 71 int board_eth_init(bd_t *bis) 72 { 73 int error = 0; 74 75 #ifdef CONFIG_SMC91111 76 error = smc91111_initialize(0, CONFIG_SMC91111_BASE); 77 #endif 78 79 #ifdef CONFIG_FSL_MC_ENET 80 error = cpu_eth_init(bis); 81 #endif 82 return error; 83 } 84 85 #ifdef CONFIG_FSL_MC_ENET 86 void fdt_fixup_board_enet(void *fdt) 87 { 88 int offset; 89 90 offset = fdt_path_offset(fdt, "/soc/fsl-mc"); 91 92 /* 93 * TODO: Remove this when backward compatibility 94 * with old DT node (/fsl-mc) is no longer needed. 95 */ 96 if (offset < 0) 97 offset = fdt_path_offset(fdt, "/fsl-mc"); 98 99 if (offset < 0) { 100 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", 101 __func__, offset); 102 return; 103 } 104 105 if (get_mc_boot_status() == 0) 106 fdt_status_okay(fdt, offset); 107 else 108 fdt_status_fail(fdt, offset); 109 } 110 #endif 111 112 #ifdef CONFIG_OF_BOARD_SETUP 113 int ft_board_setup(void *blob, bd_t *bd) 114 { 115 u64 base[CONFIG_NR_DRAM_BANKS]; 116 u64 size[CONFIG_NR_DRAM_BANKS]; 117 118 ft_cpu_setup(blob, bd); 119 120 /* fixup DT for the two GPP DDR banks */ 121 base[0] = gd->bd->bi_dram[0].start; 122 size[0] = gd->bd->bi_dram[0].size; 123 base[1] = gd->bd->bi_dram[1].start; 124 size[1] = gd->bd->bi_dram[1].size; 125 126 fdt_fixup_memory_banks(blob, base, size, 2); 127 128 #ifdef CONFIG_FSL_MC_ENET 129 fdt_fixup_board_enet(blob); 130 fsl_mc_ldpaa_exit(bd); 131 #endif 132 133 return 0; 134 } 135 #endif 136